Communications systems can use the Advanced Switching Interconnect (ASI) as a Swiss army knife for both chip- and board-level links handling control- and data-plane traffic. ASI can replace a variety of standard and proprietary technologies to streamline backplane design, enhance interoperability among cards from multiple vendors, enable backplane-level quality-of-service (QoS) functions and enhance system scalability.
The evolution of communications system architectures in recent years has been driven primarily by the need for speed, with line card designs often leading the way. Many chip-to-chip standards have emerged, such as System Packet Interface 4 (SPI-4) for network processing unit (NPU)-to-framer connections and the Common Switch Interface (CSIX) for NPU-to-fabric interfaces linking high-speed framers, media access controllers (MACs), NPUs, traffic managers and other chips.
However, there are no firm standards in place for backplane interconnects.
Various switch fabric chip-set vendors have developed a number of proprietary board-level protocols. These dedicated physical links, running at 2.5 Gbits/second or 3.125 Gbits/s, are essentially fixed-function implementations that are designed to move data quickly but that limit overall flexibility.
These proprietary backplane approaches mean that system configurations are limited to only those line cards and special-function cards that support the specific physical protocol. In addition, these backplane technologies typically do not handle control-plane communications between line card CPUs and system-level CPUs. As a result, most designers opt to use higher-level Ethernet protocols across the backplane for control-plane functions.
In contrast, ASI gives developers a foundation, based on the serial PCI Express interconnect, for implementing multipoint, peer-to-peer switched interconnect links, which can handle both data-plane and control-plane communications. Therefore, ASI overcomes the limitations of proprietary approaches for data flow and allows more efficient system-level control without the overhead of using Ethernet.
Elimination of the redundant Ethernet control plane and associated drivers also reduces power requirements on line cards and control cards, thereby allowing more functionality to be packed within tight system-level power constraints. In addition, reducing the overall number of backplane traces can lessen the risks of signal crosstalk and curtail the electromagnetic interference noise generated by the system.
Each line card can include a local ASI switch element that contains links to the on-board framers, MACs, NPUs and CPUs as well as to other devices such as specialized traffic managers or data encryption engines. External interfacing for both data and control can then be implemented via the same ASI communications links, thereby reducing component count, on-board circuit complexity and the number of required backplane traces.
While ASI uses the same physical-link and data-link layers as the PCI Express standard to take advantage of the large PCI ecosystem, it also adds specific enhancements that support the flow of high-speed communications-oriented data.
With an increasing number of line-card designers first incorporating PCI Express interfaces and then adding in ASI capabilities to their offerings, the current barriers of interoperability will be lowered and eliminated. Instead of having to choose from just line cards, control cards and special function modules that support a particular proprietary backplane interconnect, network administrators will have much more flexibility to configure systems to meet exact requirements by mixing best-of-class cards from different vendors. Further, this will help drive overall costs down because card vendors will not have to support multiple designs for different backplanes.
The ASI physical layer, as borrowed from PCI Express, allows on-board data links to be scaled to much higher bandwidths than can be achieved with existing chip-to-chip interfaces such as SPI-4, the Network Processor Streaming Interface or CSIX. For example, at higher data rates, SPI-4 interfaces may require complex and expensive dynamic phase alignment in order to maintain signal-timing relationships.
In contrast, the PCI Express physical layer used in ASI can deliver much higher data rates across long backplane traces simply by adding additional channels without the need for dynamic phase alignment.
Perhaps more important, ASI also opens the way to use the same interconnect technology across chip-to-chip, board-to-board, backplane level and even for short-haul interchassis communications. This offers significant design and configuration flexibility at every level. Board-level designers will no longer be constrained by the limitations of managing high-speed traces within a single board and instead can more easily opt for segmenting portions of the functionality on to mezzanine boards as appropriate.
To deliver on sustained performance objectives, communications systems need to assure predictable latency for both data flow and control functions. ASI provides a "virtual channel" mechanism with a high degree of flexibility for isolating and controlling various traffic flows across the ASI switch fabric. In this way, ASI provides a superset of the QoS features that are found in proprietary fabrics today.
Control traffic can be routed via bypassable virtual channels (BVCs) while data traffic is routed via ordered virtual channels (OVC) or multicast virtual channels (MVCs), with additional flexibility for multiple traffic classes and subchannels within each channel type. At each fabric stage, the various traffic flows are scheduled through to the next stage using strict priority, round-robin or weighted round-robin mechanisms.
For quality-of-service purposes, traffic classes can be assigned at the fabric endpoints to differentiate traffic flows. For example, in a typical communications system, there could be one BVC for control and multiple OVCs and/or MVCs for data, each with isolated virtual channel queues. All packets are forwarded through the fabric by utilizing the traffic class field in the ASI header, with mapping occurring between classes and virtual channels at each fabric stage.
This combination of dedicated VCs and scheduling options allows the ASI fabric to automatically manage various flows through the fabric and provides such capabilities as guaranteeing maximum latency or minimum bandwidth for any given traffic class.
Gary Lee (firstname.lastname@example.org) is director of switch-fabric marketing at Vitesse Semiconductor Corp. (Camarillo, Calif.).
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