System-in-package becomes SoC alternative

Many design teams are taking a harder look at the system-in-package alternative to conventional system-on-chip design. The advantages of combining multiple dice in one package have been well-documented. The SiP approach exploits the low cost and rigorous testing of commodity ICs such as DRAMs. It allows specialized circuitry, such as RF amplifiers or precision analog components, to reside on their own dice, fabricated in their own optimized processes. It can integrate high-quality passive components into the package, reducing parts count and board area in ways the SoC cannot. Compared with a complex SoC design, it can cut design risk and shorten time-to-volume production, especially if that design would require a large die area or a leading-edge process. And it can lever existing IC designs that are already in production, well up the yield curve and field-tested. But combining several dice into a single package is not simply a matter of ordering a different package option from the assembly vendor. The SiP assembly itself becomes a design project, with all of the mechanical, electrical and thermal issues that any other new package design would entail. But in the case of an SiP there are added complexities.