Making Converter Integration Happen in Mobile Phone SoCs
Yves Gagnon, LTRIM
Aug 05, 2004 (6:00 AM)
Figure 1: Diagram showing a typical voltage reference circuit.
In order to interface with the "real world", cell phones require system-on-a-chip (SoC)-level integration of high-performance digital-to-analog (DAC) and/or analog-to-digital (ADC) conversion IP blocks. ADC and DAC converter blocks must also be coupled with high-accuracy, low-noise voltage-reference circuits.
The problem, however, is that high-performance voltage references used for ADC/DAC are mainly offered in a discrete component form. But adding another component such as a voltage reference to the mix doesn't help a designer keep the size of a cell phone down. Therefore, the challenge for semiconductor companies is to integrate as many analog mixed-signal and digital functions into a single system-on-a-chip (SoC) as possible.
While it may seem that voltage reference intellectual property (IP) is the obvious answer to a complete DAC/ADC solution, it is not easy to integrate. The IP is subject to the same accuracy issues as discrete voltage reference ICs. On top of this, for tolerances less than 0.5%, post-manufacturing tuning must be used.
Voltage reference IP poses further difficulties. For one, the quality of the mixed-signal design kit is very important. And secondly, the substrate coupling between the different IP blocks must be addressed.
But don't fear. Complete SoC integration of DAC/ADC IP coupled with high-performance voltage reference IP can be achieved. This article will show designers how.
Tight Output Tolerances
The accuracy of the DAC/ADC is directly affected by the tolerance of the voltage reference. In order to achieve the accuracy needed in applications such as wireless devices, the accuracy and therefore, the tolerance of the voltage reference must be designed tight.
As indicated in the typical shunt voltage reference circuit shown in Figure 1, several resistor and transistor components must be matched to allow for tight output tolerances and post manufacturing resistor tuning must also take place.
There are several tuning techniques that are widely used in the industry today that are used for discrete (off-chip) solutions, including thin-film, thick-film resistor deposits, electric, and laser fuse blowing. These techniques, however, are not entirely suitable for IP.
The tuning techniques used require complete compatibility with CMOS manufacturing process, (and as an aside, it should not require additional steps to CMOS manufacturing process). The tuning technique must not change the normal SoC design flow. It has to occupy a very small silicon area, and it must not require additional I/Os.
To accomplish this, an accurate control the dopant concentration profile in standard diffused resistors must be achieved using the heating effects of a laser. A typical application of this technique is shown in Figure 2, which is a type of U-shaped structure made of diffused resistors.
Figure 2: Diagram showing a U-shaped diffused resistor.
The laser beam shown in Figure 2 heats the channel in between the diffused resistor structures. Heat from the laser beam creates a melted silicon area that encompasses both diffused resistor regions and creates an electrical link by diffusing the dopants within the channel. By so doing, designers short-circuit a part of the diffused resistors structure with a low resistance path as shown in Figure 2. By accurately controlling the physical parameters of the laser beam, a very tight tolerance resistance adjustment can be achieved.
Dealing with Temperature Variations
Temperature has a big factor in the performance of analog circuits, and in application such as cell phones where they need to operate in areas where the environment is not very friendly, the effects of the temperature variations need to be accounted for and addressed.
Another important characteristic of a high-performance CMOS voltage reference IP is managing the output voltage stability over temperature variations. In a voltage reference IP designs, the lower the temperature coefficient, the higher the output voltage stability. The lowest temperature coefficient is obtained through optimizing the design of the band-gap core as shown in Figure 1.
In pure CMOS technologies, a band-gap core is designed using parasitic bipolar transistors that are not, most of the time, very well modeled in most of pure play foundry design kits. Therefore, a designer must enhance the readily available mixed-signal models in order to provide low-temperature coefficient CMOS voltage reference IP. In order to do so, accurate physical characterization of bipolar transistor on silicon has to be done, and the results are fed back to the model to re-optimize it
Place and Route Rules
In a system such as a cell phone, where digital, analog and power consuming circuits must co-exist, interference is a big concern. Designers, therefore, must take care to reduce undesired interference between different digital IP blocks and the voltage reference IP block.
For example, substrate noise generated by digital blocks or temperature gradient generated by power consuming IP blocks can affect the accuracy and the performance of the voltage reference IP. To avoid such interference, design placement and routing rules should be applied. These rules include:
1. The Use deep N-well layers available in most CMOS technologies to reduce coupling between NMOS transistors and the substrate. Another rule is to systemically use double-guard rings to isolate sensitive voltage reference IP from the surrounding noisy circuits.
2. For placement, the accuracy of the analog IP, such as voltage reference can be affected by noise. Today's cellular handset chips run at very high frequencies. The digital circuits are then switching at a very high rate and induce a lot of noise. The accuracy and performance of the analog IP is affected by this noise and therefore should not be placed near fast switching digital IP, if possible.
In addition the accuracy of analog circuits such as voltage reference can be significantly affected by mechanical stress induced in the silicon substrate during the packaging process. However, since such stress is much higher in the periphery of the die, placing the voltage reference block as close as possible to the center of the chip will reduce the effect of mechanical stress. Also, sensitive circuitry such as a voltage reference should be kept away from temperature generating blocks or hotspots.
3. For routing, it is always suggested to use separate power and ground lines for digital and analog circuits. Routing over sensitive voltage reference IP blocks can induce mechanical stress that will affect the accuracy of the voltage reference block. The connection between the output of the voltage reference and the load should have a very low parasitic resistance (large metal line) to optimize the load regulation that can affect the accuracy of the output voltage.
Complete SoC integration of DAC/ADC IP coupled with high-performance voltage reference IP can be achieved, even though it is not easy to integrate. To make this happen, designers must follow design, placement, and routing rules; take care to match resistors and transistor components; utilize laser tuning; and manage temperature variations. By offering a completely integrated SoC that comprises all DAC/ADC elements, including a voltage reference, smaller cell phone designs can be made a reality.
About the Author
Yves Gagnon is the founder and chief technology officer at LTRIM Technologies. Yves is a physics engineer who graduated from Montreal's Ecole Polytechnique. He can be reached at firstname.lastname@example.org.
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