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Multi Protocol Endpoint IP Core for Safe and Secure Ethernet Network
Collaboration Makes New Commercial Ultra Low-Power Solution Accessible To Designers
By Johan van Ginderdeuren, Philips Digital Systems Labs, Leuven, Belgium
A successful new collaboration between Synopsys and Philips means designers around the world can now gain access to a new digital signal processor (DSP) core. Created specifically for ultra-low-power consumer audio applications, the Philips Electronics' ultra-low-power CoolFlux DSP core provides a standard platform that significantly reduces the power consumption of portable audio devices such as MP3 players, digital hearing aids and headsets while allowing for high audio quality.
Created by Philips Digital System Labs, a founding member of the DSP Valley technology networking organization, CoolFlux DSP is easy to program. The software development kit provided by Philips and its DSP Valley partner Target Compiler Technologies, includes an optimizing C compiler, assembler, instruction set simulator and graphical debugger, and applied retargetable compilation technology to ensure efficient C-level programmability, which was a key design goal.
Unique Delivery and Support
CoolFlux DSP is exclusively distributed and supported by Synopsys for Synopsys customers and is now available to more than 25,000 DesignWare Library users through the Synopsys DesignWare® Star IP program. The Star IP program was created to provide developers with high-performance, high-value IP from leading IP providers such as Philips, IBM, Infineon, MIPS and NEC.
As the first DSP core to be distributed through the program, the Star IP CoolFlux DSP provides a new embedded and synthesizable 24-bit DSP core, which has been optimized for use with the Galaxy Design and Discovery Verification platforms from Synopsys.
Making the CoolFlux DSP core available through Synopsys� DesignWare library marks a milestone in the evolution of a new support and distribution model that provides significant advantages for designers. In general, access to high-quality IP significantly reduces risk across the entire design process - especially critical for design teams operating for the consumer market - and enables accelerated time-to-market, reduced development costs, and enhanced reliability.
Working in close cooperation, a key priority for both Philips and Synopsys was guaranteeing that the core IP would be both dependable and fully reusable by creating an easy-to-use and reliable solution for use in complex ultra-low-power applications. The DSP core is fully compliant with the Reuse Methodology Manual (RMM). To achieve this, special consideration was given to the design hierarchy and documentation, as well as RTL coding style. In addition, Synopsys synthesized the solution to several libraries and ensured the synthesis process was meticulously tested. To facilitate reliable verification of the integrated DSP IP, the packaged core incorporates a comprehensive verification suite, and is tested with a variety of both VHDL and Verilog simulators.
Design Optimized for Low Power
In order to reduce power within the design, the RTL for the core has a significant amount of clock gating. The synthesis scripts provided with the CoolFlux DSP coreKits use Synopsys Power Compiler to add further clock gating during the implementation process. This has the additional benefit of reducing overall gate count, since shutting off the clock is a more efficient way to prevent loading a flip-flop than inserting a feedback multiplexer.
In general, synthesis scripts are optimized to reduce the area of the circuit. Philips'experience with the implementation of the CoolFlux DSP core has been that the power consumption also is reduced proportionately with the gate count.
When mapping the design to a technology library, if the library has been characterized for power, the scripts can also (optionally) use a specific Power Compiler command to enable the synthesis process to use lower-powered cells as it optimizes the circuit.
An Embedded Ultra-low Power DSP Core
Based on years of research and product experience in the field of digital audio and ultra-low-power technologies, the CoolFlux DSP core was specifically developed for portable audio encoding/decoding, sound enhancement and noise suppression. The core targets specific applications such as noise-cancelling headsets, hearing instruments, biomedical devices, and portable audio players.
Figure 1. Devices to benefit from CoolFlux DSP
The dual multiply-accumulate core enables a system clock up to135MHz, in 0.18-micron CMOS worst-case commercial conditions at 1.8V, while providing an operation level parallelism to reach up to 1000MOPS. Estimated maximum performance in 0.13-micron CMOS is 175 MHz with a 1.2V supply. A typical ultra-low-power scenario is 128 Kbps stereo MP3 decoding with voltage-scaling, consuming less than 1 mW in a 0.18-micron CMOS process.
Designed with a highly-efficient instruction-level parallelism (ILP) optimizing C compiler, the CoolFlux DSP software tool set offers an adjacent instruction-level simulator, assembler, linker and graphical debugger. The compiler is capable of exploiting all the parallelism in the core, generating highly-efficient code from both a cycle and code density perspective. Compact 32-bit instructions, as well as program memory compression techniques, ensure a small memory footprint.
Other benefits include a minimal core size of around 43K gates (plus optional debug interface of around 5k gates) and an extensive software library for audio decoding and advanced sound enhancement algorithms.
CoolFlux Key Features
- Ultra low power consumption
- < 0.1 mW/MHz @ 1.2V (0.13 � CMOS)
- < 0.2 mW/MHz @ 1.8V (0.18 � CMOS)
- Highly optimizing C-compiler
- Minimal core size (43k gates)
- Small memory footprint
- Performance:
- 175MHz (0.13 µ CMOS); > 1295 MOPs
- 135MHz (0.18 µ CMOS); > 1000 MOPs
- Extensive software library of audio decoding and advanced sound enhancement algorithms
- Debugging interface (JTAG based, 5k gates)
Hardware features include a dual Harvard architecture, full 24-bit datapaths and two 24x24-bit signed multipliers. Extensive addressing modes with modulo protection and bit reversal are supplemented by a RISC instruction set that is suitable for control, as well as DMA ports for both program and data memories. Three maskable low-latency interrupts are supplemented by extensive stop/restart instruction and power management support.
Figure 2. CoolFlux DSP Architecture
Application software is available to support pitch control, virtual sound-field rendering for headphones and speakers, audio beam forming, speech recognition and intelligibility improvement along with echo and noise cancellation. Supporting audio codecs such as MP3, SBC and G722, the CoolFlux DSP also provides full duplex 'hands-free' processing.
Smooth Collaboration Generates Commercial Gains
Access to CoolFlux DSP technology through the Star IP program offers an ultra low-power, audio industry-standard processor solution on which to develop new, advanced products. The highly effective and productive cooperation between the IP team at Synopsys and the Philips design team demonstrated how captive corporate IP can be unlocked for a broad market.
As a lead adopter of the CoolFlux DSP core technology, Dspfactory, a leading developer of digital chips for hearing aids, plans to incorporate the core within future chip sets in order to offer customers a platform that is feature-rich, extremely flexible and ultra-low-power.
Available to DesignWare Library Users
Distributed as a DesignWare coreKit, the CoolFlux DSP core is packaged with coreBuilder and is delivered with coreConsultant to automate the verification and synthesis processes for the core. The Design Views coreKit, including simulation and timing models with complete documentation, are available free to DesignWare Library licensees (www.synopsys.com/dwrequest). The Implementation Views coreKit, which includes the synthesizable RTL, can be obtained from Philips, via its technology licensing division, Philips Intellectual Property and Standards (Philips IP&S) and is delivered and supported by Synopsys.
Johan van Ginderdeuren
Johan van Ginderdeuren, with Philips since 1986 in various VLSI and DSP design-related functions, with 25 years of field experience, is currently program manager at Philips Digital Systems Labs, responsible for its Wearable Ultra Low Power Systems program, which includes the CoolFlux DSP activities.
About Royal Philips Electronics
Royal Philips Electronics of the Netherlands (NYSE: PHG, AEX: PHI) is one of the world�s biggest electronics companies and Europe�s largest, with sales of EUR 29 billion in 2003. It is a global leader in color television sets, lighting, electric shavers, medical diagnostic imaging and patient monitoring, and one-chip TV products. Its 165,300 employees in more than 60 countries are active in the areas of lighting, consumer electronics, domestic appliances, semiconductors, and medical systems. News from Philips is located at www.philips.com/newscenter.
