English
The Importance of Thorough Signal Integrity Analysis - A Signal Integrity Case Study
By John Ellis, Co-Founder and VP, Signal Integrity, TriCN
Introduction
In order to guarantee a successful system power-up, Signal Integrity (SI) analysis must be a required element of the system implementation. Unfortunately, for some companies, an appreciation of SI analysis occurs only after having failed to perform it. The reasons for not performing SI analysis vary from constrained resources (especially for young semiconductor companies trying to stretch their VC funding), or a poor grasp of the merits of the analysis. This can come from inexperience with higher-speed interfaces and the techniques required for dealing with them, or a perception that the performance demands of the proposed interfaces are low enough so as not to require SI analysis. In this situation, while it is possible to achieve successful power-up, the odds (and costs) of failure are high enough to warrant performing the analysis. The extra time and money spent on SI pales in comparison to the cost of re-engineering and re-spinning the chip to account for the errors in the original design.
Case Study
The following case study analyzes such a situation. The chip design in question incorporated a 167Mhz DDR memory interface with a single load on the data and strobe nets. What should have been a fairly straightforward implementation turned out to be problematic on power-up.
TriCN¡¯s forensic analysis of the problem identified several sources of the poor SI performance. TriCN suggested solutions, which were implemented by the customer, and the system worked the second time. With analysis on the front end, most of these problems would have been caught and avoided in the first design cycle, saving time and money.
Problem Definition
The customer approached TriCN for help after they implemented TriCN¡¯s SSTL-2 I/Os in their DDR interface. They experienced three distinct problems they wished to diagnose and correct.
1. There was a significant notch in the center of the received DQS signal threatening threshold violations at the load.
2. Both DQS and DQ were having trouble reaching full swing at the controller pad as a result of reflections from the net. This resulted in the cell increasing current draw during the transition times and spending almost no time in the low current state
3. After tri-stating the nets, a significant bump with potential threshold violations was received at the load.
The analysis TriCN undertook demonstrated that far from being distinct, these problems were interrelated and could have been avoided with thorough analysis on the front end.
Figure 1 below is a schematic of the interface being analyzed. (Note: This case study is only concerned with the Write timing. Since this is a bi-directional interface, any changes made to the interface should be analyzed for the Read commands as well.) The analysis looks at how the toggling of the 8 DQ lines impact the signal integrity of the DQS. The net is approximately 8.25¡± long routed in strip-line with an ¥åR of 3.7. There is a flip chip package at the controller and a TSOP package at the DRAM. A discrete series resistor of 16.5§Ù is placed at the output of the DQS and DQ controller package. The DQS also has a parallel termination of 53 Ohms to 0.73V at the DRAM end of the net. The termination to 0.73V was an attempt by the end user to address a ¡°bump¡± in DQS when the nets were tri-stated. The purpose was to keep the bump from breaking threshold.
Figure 1: Schematic of DQS, DQ interface under analysis.
The first problem to be addressed is shown in figure 2. This is a screen shot of the waveforms taken at the output pad of the controller. It shows a distinct glitch in the center of the DQS waveform that coincides with the 0 to 1 toggling of the DQ lines. This dip is causing the DQS to delay reaching full swing as more current must be drawn for the output to overcome the glitch shown.
Figure 2: Glitch introduced on DQS by 8 DQ lines toggling from 0 to 1.
The second problem to be addressed is a glitch on a ¡°quiet¡± DQS line that occurs shortly after the nets have been tri-stated by the controller. This glitch has led to occasional false switching as it can exceed the Vref level. It also coincides with significant oscillation on the DQ lines after tri-state. This is illustrated in figure 3.
Figure 3: Glitch on DQS after net tri-stated, coincides with oscillation on DQ.
Fixing the Glitch in DQS The glitch found on the DQS signal at the pad when DQS is held high and the DQ lines switch from high to low is predominantly from inductance in the VD33 and VSSPST power paths from the board up through the package. It is a result of package and board inductance, poor decoupling and a resonant condition on the overall net. Figure 4 is an illustration of how the ripple on the Vsspst and the Vd33 rails coincide with the dip within DQS.
Figure 4: Ripple on Vsspst and DQS as it corresponds to glitch in DQS signal.
Package Inductance The package implemented was flip chip, which is a reasonable package for this application. An 8:1 signal to power/ground ratio was used which is consistent with TriCN¡¯s recommendations. One problem detected was that the 2.5V plane in the board was in layer 18 of a 20 layer, 0.125¡± thick board. Since the customer was planning to re-spin the board, he was able to relocate this plane to layer 4, reducing the via inductance in the Vdd path. This resulted in a reduction in the depth of the dip on the order of 50 to 10 mV. This improvement is shown in figure 5. Note that figure 5 was taken at the load at the far end of the net. This was done because this change was difficult to see at the near end because of the other sources of ripple described above, particularly reflections on the net.
Figure 5: Improvement of dip from relocating power plane in PCB.
Decoupling Capacitance During the implementation phase, the customer had left on only a small amount of room for surface mounted decoupling on the package. For the 8 DQ lines switching and 1 DQS line in the simulation, a single 0402 2nF capacitor surface mounted on the package was shown to provide significant improvement in the depth of the dip in the DQS signal. The capacitor modeled had an ESL of 0.5 nH and was placed across the VD33 and VSSPST planes on the package. Figure 6 shows 500 mV to 769 mV improvement in the magnitude of the dip across PVT corners. The amount of this improvement was significant leading the customer to seriously consider re-spinning the package to accommodate this discrete capacitance for all 128 bits of the two interfaces.
Figure 6: Improvement in voltage dip through the addition of a 2nF decoupling capacitor.
Resonant Length
Exacerbating the problem is the total routed length of the board. At 8.25¡±, the total roundtrip time of a reflected signal on the board is approximately 2.7ns. When package delays are included, the overall roundtrip time is very close to 3.0 ns, or ½ of one clock period at 166.7 MHz. Therefore, as the bits are trying to switch, a reflection from the previous transition arrives at the pad from the un-terminated DQ loads. It then requires more current draw to overcome this reflection at the pad. Either increasing or decreasing the board length can reduce the dip on the order of 100 mV in magnitude.
Tri-State Bump Effect
A tri-state bump effect occurs when the OEN is placed into its tri-state condition, generating a bump on the quiet DQS line that can violate the switching threshold levels. The customer tried to address this effect by terminating the DQS net to 0.76V at the far end instead of 1.25V. This seemed to produce a resonance effect in combination with power ground inductance effects. Figure 7 shows that the timing of the OEN signal has a dramatic effect on the DQ pad.
In the top case, the OEN period was set to 54ns, the cell to tri-state 1.91 ns. after the last DQ bit toggles low. This sets up an oscillation on the DQ lines, the first edge of which creates a perturbation on the power/ground circuit that creates a bump on the DQS line that can cause timing glitches. By increasing the OEN period to 58 ns., the oscillation goes away, as does the bump on the DQS.
Figure 7: OEN timing creating DQ oscillation and resulting bump on DQS. Only one DQ toggling in this case.
To get a better look at what is going on, the frequency of the interface was reduced. Figure 8 is essentially the same net, but run at ¼ frequency. It shows that there is a plateau of ~3ns width on the DQ lines due to reflections. When the OEN toggles before the DQ has reached a defined level, the output of the DQ resonates. Increasing the tri-state delay or reducing the routed length gives the DQ pad adequate time to resolve and avoids the resonant condition.
Figure 8: OEN toggles before DQ plateau resolves causing resonant behavior on the output.
Conclusions
The forensic SI analysis was able to determine the sources of noise on the DQS and offer solutions. Much of the problem was exacerbated by the selection of a resonant length for the PCB route. The reflections received back at the driver caused and increase in power rail ripple, deepening the notch in the DQS line. These same reflections caused the I/O cell to perpetually be in a state of sourcing or sinking current. The OEN toggle, which occurred during a reflection induced transition plateau for the DQ at the pad caused the output to oscillate, generating the tri-state bump at the far end of the net.
The customer was able to make changes to the board stack-up and to the routed length of the nets to effect some improvement. The surface mount decoupling of the package proved too difficult to implement this late in their design cycle.
If a thorough signal integrity analysis had been undertaken at the front end, all of the recommended changes could have been implemented in the beginning of the design process, or other solutions could have been reached. It would have cost the company a few thousand dollars and 2-4 weeks in the design cycle. By not performing SI analysis, the company was forced to spend hundreds of thousands of dollars for re-spin, and delay the launch of their product by several months.
This case study illustrates that SI analysis is a cost effective insurance policy to guard against the failure of a product, and potentially the downfall of a company.
Introduction
In order to guarantee a successful system power-up, Signal Integrity (SI) analysis must be a required element of the system implementation. Unfortunately, for some companies, an appreciation of SI analysis occurs only after having failed to perform it. The reasons for not performing SI analysis vary from constrained resources (especially for young semiconductor companies trying to stretch their VC funding), or a poor grasp of the merits of the analysis. This can come from inexperience with higher-speed interfaces and the techniques required for dealing with them, or a perception that the performance demands of the proposed interfaces are low enough so as not to require SI analysis. In this situation, while it is possible to achieve successful power-up, the odds (and costs) of failure are high enough to warrant performing the analysis. The extra time and money spent on SI pales in comparison to the cost of re-engineering and re-spinning the chip to account for the errors in the original design.
Case Study
The following case study analyzes such a situation. The chip design in question incorporated a 167Mhz DDR memory interface with a single load on the data and strobe nets. What should have been a fairly straightforward implementation turned out to be problematic on power-up.
TriCN¡¯s forensic analysis of the problem identified several sources of the poor SI performance. TriCN suggested solutions, which were implemented by the customer, and the system worked the second time. With analysis on the front end, most of these problems would have been caught and avoided in the first design cycle, saving time and money.
Problem Definition
The customer approached TriCN for help after they implemented TriCN¡¯s SSTL-2 I/Os in their DDR interface. They experienced three distinct problems they wished to diagnose and correct.
1. There was a significant notch in the center of the received DQS signal threatening threshold violations at the load.
2. Both DQS and DQ were having trouble reaching full swing at the controller pad as a result of reflections from the net. This resulted in the cell increasing current draw during the transition times and spending almost no time in the low current state
3. After tri-stating the nets, a significant bump with potential threshold violations was received at the load.
The analysis TriCN undertook demonstrated that far from being distinct, these problems were interrelated and could have been avoided with thorough analysis on the front end.
Figure 1 below is a schematic of the interface being analyzed. (Note: This case study is only concerned with the Write timing. Since this is a bi-directional interface, any changes made to the interface should be analyzed for the Read commands as well.) The analysis looks at how the toggling of the 8 DQ lines impact the signal integrity of the DQS. The net is approximately 8.25¡± long routed in strip-line with an ¥åR of 3.7. There is a flip chip package at the controller and a TSOP package at the DRAM. A discrete series resistor of 16.5§Ù is placed at the output of the DQS and DQ controller package. The DQS also has a parallel termination of 53 Ohms to 0.73V at the DRAM end of the net. The termination to 0.73V was an attempt by the end user to address a ¡°bump¡± in DQS when the nets were tri-stated. The purpose was to keep the bump from breaking threshold.
Figure 1: Schematic of DQS, DQ interface under analysis.
The first problem to be addressed is shown in figure 2. This is a screen shot of the waveforms taken at the output pad of the controller. It shows a distinct glitch in the center of the DQS waveform that coincides with the 0 to 1 toggling of the DQ lines. This dip is causing the DQS to delay reaching full swing as more current must be drawn for the output to overcome the glitch shown.
Figure 2: Glitch introduced on DQS by 8 DQ lines toggling from 0 to 1.
The second problem to be addressed is a glitch on a ¡°quiet¡± DQS line that occurs shortly after the nets have been tri-stated by the controller. This glitch has led to occasional false switching as it can exceed the Vref level. It also coincides with significant oscillation on the DQ lines after tri-state. This is illustrated in figure 3.
Figure 3: Glitch on DQS after net tri-stated, coincides with oscillation on DQ.
Fixing the Glitch in DQS The glitch found on the DQS signal at the pad when DQS is held high and the DQ lines switch from high to low is predominantly from inductance in the VD33 and VSSPST power paths from the board up through the package. It is a result of package and board inductance, poor decoupling and a resonant condition on the overall net. Figure 4 is an illustration of how the ripple on the Vsspst and the Vd33 rails coincide with the dip within DQS.
Figure 4: Ripple on Vsspst and DQS as it corresponds to glitch in DQS signal.
Package Inductance The package implemented was flip chip, which is a reasonable package for this application. An 8:1 signal to power/ground ratio was used which is consistent with TriCN¡¯s recommendations. One problem detected was that the 2.5V plane in the board was in layer 18 of a 20 layer, 0.125¡± thick board. Since the customer was planning to re-spin the board, he was able to relocate this plane to layer 4, reducing the via inductance in the Vdd path. This resulted in a reduction in the depth of the dip on the order of 50 to 10 mV. This improvement is shown in figure 5. Note that figure 5 was taken at the load at the far end of the net. This was done because this change was difficult to see at the near end because of the other sources of ripple described above, particularly reflections on the net.
Figure 5: Improvement of dip from relocating power plane in PCB.
Decoupling Capacitance During the implementation phase, the customer had left on only a small amount of room for surface mounted decoupling on the package. For the 8 DQ lines switching and 1 DQS line in the simulation, a single 0402 2nF capacitor surface mounted on the package was shown to provide significant improvement in the depth of the dip in the DQS signal. The capacitor modeled had an ESL of 0.5 nH and was placed across the VD33 and VSSPST planes on the package. Figure 6 shows 500 mV to 769 mV improvement in the magnitude of the dip across PVT corners. The amount of this improvement was significant leading the customer to seriously consider re-spinning the package to accommodate this discrete capacitance for all 128 bits of the two interfaces.
Figure 6: Improvement in voltage dip through the addition of a 2nF decoupling capacitor.
Resonant Length
Exacerbating the problem is the total routed length of the board. At 8.25¡±, the total roundtrip time of a reflected signal on the board is approximately 2.7ns. When package delays are included, the overall roundtrip time is very close to 3.0 ns, or ½ of one clock period at 166.7 MHz. Therefore, as the bits are trying to switch, a reflection from the previous transition arrives at the pad from the un-terminated DQ loads. It then requires more current draw to overcome this reflection at the pad. Either increasing or decreasing the board length can reduce the dip on the order of 100 mV in magnitude.
Tri-State Bump Effect
A tri-state bump effect occurs when the OEN is placed into its tri-state condition, generating a bump on the quiet DQS line that can violate the switching threshold levels. The customer tried to address this effect by terminating the DQS net to 0.76V at the far end instead of 1.25V. This seemed to produce a resonance effect in combination with power ground inductance effects. Figure 7 shows that the timing of the OEN signal has a dramatic effect on the DQ pad.
In the top case, the OEN period was set to 54ns, the cell to tri-state 1.91 ns. after the last DQ bit toggles low. This sets up an oscillation on the DQ lines, the first edge of which creates a perturbation on the power/ground circuit that creates a bump on the DQS line that can cause timing glitches. By increasing the OEN period to 58 ns., the oscillation goes away, as does the bump on the DQS.
Figure 7: OEN timing creating DQ oscillation and resulting bump on DQS. Only one DQ toggling in this case.
To get a better look at what is going on, the frequency of the interface was reduced. Figure 8 is essentially the same net, but run at ¼ frequency. It shows that there is a plateau of ~3ns width on the DQ lines due to reflections. When the OEN toggles before the DQ has reached a defined level, the output of the DQ resonates. Increasing the tri-state delay or reducing the routed length gives the DQ pad adequate time to resolve and avoids the resonant condition.
Figure 8: OEN toggles before DQ plateau resolves causing resonant behavior on the output.
Conclusions
The forensic SI analysis was able to determine the sources of noise on the DQS and offer solutions. Much of the problem was exacerbated by the selection of a resonant length for the PCB route. The reflections received back at the driver caused and increase in power rail ripple, deepening the notch in the DQS line. These same reflections caused the I/O cell to perpetually be in a state of sourcing or sinking current. The OEN toggle, which occurred during a reflection induced transition plateau for the DQ at the pad caused the output to oscillate, generating the tri-state bump at the far end of the net.
The customer was able to make changes to the board stack-up and to the routed length of the nets to effect some improvement. The surface mount decoupling of the package proved too difficult to implement this late in their design cycle.
If a thorough signal integrity analysis had been undertaken at the front end, all of the recommended changes could have been implemented in the beginning of the design process, or other solutions could have been reached. It would have cost the company a few thousand dollars and 2-4 weeks in the design cycle. By not performing SI analysis, the company was forced to spend hundreds of thousands of dollars for re-spin, and delay the launch of their product by several months.
This case study illustrates that SI analysis is a cost effective insurance policy to guard against the failure of a product, and potentially the downfall of a company.
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