FPGA use in software-defined radios

Software-defined radios (SDRs) are wireless devices with a reconfigurable hardware platform that can be used across multiple communications standards. As such, they can play a pivotal role in the final realization of cognitive radios. In the meantime, SDRs are rapidly becoming the de facto standard in the military, public safety and commercial wireless worlds due to their lower cost, greater flexibility and higher performance.

One key reason for SDR's growing commercial popularity is its ability to perform both the baseband processing for multiple waveforms, as well as digital intermediate frequency (IF) processing. IF processing extends the scope of digital signal processing (DSP) beyond the baseband domain, out the antenna to the RF domain. This ability to support both baseband and IF processing increases system flexibility, while also reducing manufacturing costs.

Baseband processing

Wireless standards are continuously evolving to support higher data rates through the introduction of advanced baseband processing techniques, such as adaptive modulation and coding, space-time coding (STC), beam forming, and multiple input/multiple output (MIMO) antenna techniques. Baseband signal processing devices require enormous processing bandwidth to support the computationally intensive algorithms used in these techniques. The U.S. military's Joint Tactical Radio System (JTRS), for example, defines over 20 different waveforms supported on military radios. The computational power required for some of the more complex waveforms is in the hundreds of millions of instructions per second (MIPS) on a standard processor, or thousands of logic elements (LEs) if implemented in a field programmable gate array (FPGA).

Coprocessing features

SDR baseband processing often requires both processors and FPGAs. In such applications, the processor handles system control and configuration functions, while the FPGA implements the computationally intensive signal-processing data path and control, minimizing the latency in the system. When it is necessary to switch from one standard to another, the processor can switch dynamically between major sections of software, while the FPGA can be completely reconfigured, as necessary, to implement the data path for the particular standard.

FPGAs can be used as co-processors to interface with DSPs and general-purpose processors, thereby providing higher system performance and lower system costs. Having the freedom to choose where to implement baseband-processing algorithms adds another dimension to the flexibility when implementing SDR algorithms.

The baseband components also must be flexible enough to enable the SDR to support migration between enhanced versions of the same standard, as well as support completely different standards. Programmable logic, coupled with a soft-core processor and IP blocks, provides remote upgradeability in the field. For example, an FPGA can be easily reconfigured to support the baseband transmit functions for either WCDMA/HSDPA (High-Speed Downlink Packet Access) or 802.16a standards through IP functions such as the Turbo encoder, Reed-Solomon encoder, symbol interleaver, symbol mapper and inverse fast Fourier transform (IFFT).

Digital IF processing

Digital frequency conversion offers higher performance than traditional analog radio approaches. FPGAs provide a highly flexible and integrated platform on which to implement computationally intensive digital IF functions at reasonable power — a critical factor in portable systems. IF functions that can be implemented on an FPGA include digital upconverters (DUCs) and downconverters (DDCs), as well as digital pre-distortion (DPD) and crest factor-reduction (CFR), which help to lower the cost and power of the power amplifier (PA)

Digital upconverter

Data formatting — often required between the baseband processing elements and the upconverter — can be seamlessly added at the front end of the upconverter. This technique provides a fully customizable front end to the upconverter and allows for channelization of high-bandwidth input data. Custom logic or a soft-core embedded processor can be used to control the interface between the upconverter and the baseband-processing element implemented in the FPGA.

In digital upconversion, the input data is baseband filtered and interpolated before it is quadrature-modulated with a tunable carrier frequency. To implement the interpolating baseband finite impulse response (FIR) filter, speed-area trade-offs must be made to find the optimal fixed or adaptive filter architectures for a particular standard. Numerically controlled oscillator cores can also be used to generate a wide range of architectures with spurious-free dynamic ranges in excess of 115 dB and very high performance. Depending on the number of frequency assignments to be supported, multiple digital upconverters can be easily instantiated in an FPGA.

Crest-factor reduction

Third-generation (3G) code-division multiple-access (CDMA)-based systems and multicarrier systems such as orthogonal frequency division multiplexing (OFDM) exhibit signals with high peak-to-average ratios (crest factors). Such signals drastically reduce the efficiency of power amplifiers used in the basestations. Crest-factor reduction techniques, implemented in FPGAs, are a cost-effective method for lowering the cost and complexity of the power amplifier for multiple waveform standards.

High-speed mobile data transmission employs non-constant envelope-modulation techniques such as QPSK and quadrature amplitude modulation (QAM). This places stringent linearity requirements on the PAs. Digital pre-distortion (DPD) linearization techniques, including both look-up table and polynomial approaches, can be efficiently implemented in FPGAs that contain DSP blocks. The multipliers in these DSP blocks can be run at high clock rates and can be effectively time-shared to implement complex multiplications. When used in SDR basestations, the FPGA can be reconfigured to implement the appropriate DPD algorithm that efficiently linearizes the PA used for a specific standard.

On the receiver side, digital IF techniques can be used to sample an IF signal and perform channelization and sample-rate conversion in the digital domain. Using undersampling techniques, high-frequency IF signals (typically 100+ MHz) can be quantified. Since different standards have different chip/bit rates, non-integer sample-rate conversion is required for SDR applications to convert the number of samples to an integer multiple of the fundamental chip/bit rate of any standard.

Joel Seely is a technical marketing manager at the Automotive, Industrial and Military Business Unit of Altera Corp. (San Jose, Calif.).

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