by Lauro Rizzatti Emulation and Verification Engineering (EVE)
From the ubiquitous cell phone to the digital camera to the Internet router to the car navigation system, embedded systems are permeating our daily lives. And, they continue to grow in complexity.
According to one executive from a major system house, embedded software has reached a year-to-year growth rate of 140%, compared to 40% growth in hardware contents. The dramatic shift in system-on-chip (SoC) contents is best captured in a few industry statistics. For a 20-million application specific integrated circuit (ASIC) gate design, the development budget allocated to the software team equals that assigned to the hardware team. 50% of embedded systems projects fall months behind schedule and 44% of designs meet 20% of feature and performance expectations, even when 50% of total development effort is spent in verification.
Needless to say, early software testing ahead of tapeout becomes mandatory to remain competitive, increase design quality, and shorten the time to bring new products to market.
This new scenario has prompted startups to offer software-based development environments for validating embedded applications prior to silicon availability. They all share one trait: by modeling the hardware at a high level of abstraction, above the register transfer level (RTL), they tradeoff accuracy for speed. As fast as they can execute software, they cannot catch pitfalls in the hardware/software integration—the cause of long delays to production, low-quality products and, ultimately, lost revenues and competitiveness.
The alternative is to prototype the SoC design into an field programmable gate array (FPGA)-based board. The prototype offers an accurate representation of the design—it is indeed an actual implementation in silicon, albeit not an exact replica of the final SoC. And, it runs at several megahertz, just short of real silicon.
Two choices are possible: go commercial or build it in-house. A commercial solution may have the appeal to be ready-made and to assist a broader range of design types and sizes, limited only by the largest capacity supported by the prototype. On the contrary, an in-house developed prototype typically serves only one specific design of small to medium size.
In both cases—and if truth to be told—developing an FPGA prototype with more than six or eight of the biggest FPGA devices to map a large design with vast amounts of embedded software has not been a viable approach. That's because it is a major project equivalent in engineering efforts to the creation of the design itself. Over and over again, engineers and managers complain of failing prototyping projects or of the late completion after the arrival of real silicon, thus defeating the purpose.
Several reasons lead to these failures. Setting up the design requires an uncommon level of expertise. Mapping the design in commercial or in-house developed FPGA prototypes relies on third-party tools, which often compromise features and capabilities to accommodate the widest range of systems. Or, manual techniques are used that are time-consuming, tedious to use, and error-prone.
Tasks such as design partitioning, clock tree routing, bus handling, and memory mapping—necessary to complete the mission—are complex, difficult, and unfriendly. Tasks are aggravated by the lack of visibility into the mapped design, throwing a blanket of uncertainty on the user. It has them wondering: is this a design error or a mapping error?
Occasionally, it may be possible to reproduce the problem with a hardware description language (HDL) simulator. Yet, when it occurs after several seconds of execution in the prototype or after several million cycles, it is nearly impossible to replicate and analyze the problem within an HDL simulation environment.
Drawbacks aside, the FPGA prototype well serves the embedded software developer through at least megahertz performance and relatively low price when development costs can be amortized over tens of copies.
Times have changed. The taxing restriction on design capacity of FPGA prototypes that have limited their applicability to a few FPGA devices finally has come to an end.
Designed with a new architecture around recent generations of FPGA devices, and assisted by robust and comprehensive software, a new generation of FPGA prototyping platforms has emerged. They offer a viable alternative to test embedded software on large designs with tens of million of ASIC gates, and still be used for conventional hardware verification and hardware/software integration.
These platforms consist of arrays of a relatively small number of large FPGAs, tightly coupled to a robust compiler that drastically alleviates or completely removes all of the above bottlenecks. Indeed, the design mapping process is highly automated, dramatically cutting setup time from months to days. They are fast to setup, easy to learn, and reliable. These prototyping platforms can apply a software testbench to the FPGA implementation of the design or execute embedded software at several megahertz speed. While simultaneously providing the means to read/write interactively its registers and memories, the new architecture permits designers to capture the internal state of the design in a software simulation environment at run-time without pre-compiling internal probes. These solutions allow for hardware model connectivity or intellectual property (IP) cores when simulation models aren't available. They support a level of hardware design debugging without compromising ease of use. Finally, the user can remove that uncertainty blanket and discern a design error from a mapping error.
What's more, they are priced competitively.
By providing a unified platform for hardware verification and for embedded software validation, these new generations of FPGA prototypes offer a remarkable return on investment (ROI).
At the high end of the capacity spectrum this new wave of FPGA prototypes are designed in stand-alone boxes to handle virtually any sized designs. They do not use backplanes and are quite compact, achieving the high-speed and low-cost required for software testing.
At the low end of the capacity spectrum are platforms implemented on PCI cards that plug into a PC on a designer's desktop and become personal emulation and prototyping solutions. They offer ease of use and affordability, and can be effectively deployed on small designs or on blocks that make up an SoC design.
By installing these new FPGA prototypes, a hardware design department can copy the development methodology of most software development centers. Hardware designers can test their hardware modules and a system verification team can perform system integration and carry out the time-consuming regression testing. Software developers verify their piece of code, leaving the quality assurance team to validate the entire software system.
Project teams are working on ever more complex designs that combine many interconnected blocks, including RISC processors, digital signal processors (DSPs), and co-processors. They need to debug hardware and develop software in parallel, and now have the means to do it fast, efficiently, and cost effectively. New prototyping solutions are meeting the need and creating a new era for hardware and embedded software designs.
The hardware-assisted verification market is maturing and with it comes support for more applications, along with flexible desktop solutions or more powerful standalone resources to fit every design team's requirements.
About the Author
Dr. Lauro Rizzatti is vice president of marketing and general manager of EVE-USA. He has more than 30 years of successful experience in EDA and ATE, where he held responsibilities in top management, product marketing, technical marketing, and engineering. He held various positions in companies such as Get2Chip, Synopsys, Mentor Graphics, Teradyne, Alcatel, and Italtel. Dr. Rizzatti has published several articles, viewpoints, and technical papers in the trade press and presented at a multitude of domestic and international technical conferences. He holds a doctorate in Electronic Engineering from the Universita degli Studi di Trieste, Italy.