It is clear that FPGAs are great for prototyping and low-volume production. It's also clear, however, that any relatively complex mid- to high-volume design for which power consumption, component cost and size are important issues requires another solution for mass production. That is where structured-ASIC technologies come in.
A structured ASIC is programmed in the upper levels of the fabrication process for a specific logic function. Logic not used in the circuit design is not synthesized into the structured ASIC. In most cases, that allows for use of a much smaller die that is less expensive and uses less power than the original FPGA.
ASIC memories that are embedded in structured ASICs as large blocks are faster and use less power than FPGA memories. Routing is also optimized to the shortest path between two points on the circuit based on the specific requirements of the application, further reducing the power used. Finally, multiple clocks can be used and the circuit timing optimized to find the balance between power and performance.
Considering all of these power-saving options, it is common for a structured-ASIC design to use 20 to 50 percent less power than the same design implemented in an FPGA.
There are a couple of further considerations. First, in order to match the performance of an ASIC, FPGAs must be designed in newer, more expensive processes. Thus, for a structured ASIC to match the performance of an FPGA, the ASIC technology can be at least one process generation behind the FPGA.
For example, if a design is implemented in a Xilinx Virtex-II Pro FPGA, which uses a 1.5-volt, 0.13-micron technology, the structured-ASIC replacement can be implemented in 0.18-micron or 0.15-micron technology. Implementing a design in a lower-cost, more-mature structured-ASIC technology allows for drastically reduced engineering costs.
The second impact of the smaller FPGA geometry is that smaller geometries inherently have more leakage, contributing to higher power usage. Since structured ASICs use less power, the packages used by structured-ASIC vendors need not be as complex or use as many layers as those used for FPGAs. This reduced package complexity contributes to further cost reductions.
So how can OEMs retain the low-cost, flexible development advantages of FPGAs while using structured ASICs to address the cost, power and size priorities needed for final production? The answer lies in FPGA-to-ASIC conversion methodologies developed by companies such as AMI Semiconductor.
With an effective FPGA-to-ASIC conversion, system designers can quickly get their system designed and into production using FPGA technology. Then, once the design is fully proven, the design can be rapidly and cost-effectively converted to a structured ASIC.
The low nonrecurring-engineering charges associated with a structured ASIC, coupled with the much lower unit cost, make this strategy a powerful tool in achieving low overall costs and improving competitive advantage.
To achieve the full benefit of a conversion, it is important to prototype with conversion in mind. Any differences in core voltage, for example, can be accounted for and the advanced FPGA design moved to a larger-process-geometry structured ASIC. Package requirements and board layout must be considered, bearing in mind that, even though FPGA conversion targets pin-for-pin drop-in replacement, the design may fit into a lower-pin-count package once it is migrated to an ASIC. If, for example, the production ASIC can use a lower-performance industry-standard package with lower ball counts, device costs can be further reduced over a typical drop-in replacement.
It is also important to understand long-term intellectual-property needs. Many FPGA vendors make small modifications to standard IP. Licensing agreements will prevent the designer from moving the FPGA vendor-specific IP to an ASIC, and the small modifications made to the IP mean that off-the-shelf third-party IP may not work as a drop-in replacement. If the design team believes a program will go into volume production, third-party IP should be used and a license agreement negotiated that allows IP used in the FPGA to be migrated to a structured ASIC.
The ability to convert from even the most complex FPGAs to structured ASICs is creating a symbiotic relationship between FPGA and ASIC vendors that provides OEMs with the best of both worlds-flexible and rapid development at minimal cost, combined with compact, low-power, low-cost components for final manufacture.
What's more, by planning for FPGA-to-ASIC conversion from the outset, and by working with a conversion company that can offer the necessary IP to take an FPGA prototype and convert it to a structured ASIC, it is possible to have ASICs ready as soon as FPGA-based product trials are complete, thus ensuring minimum time-to-market and maximum competitive advantage.
Vince Hopkin (Vince_Hopkin@amis.com) is vice president of structured digital products at AMI Semiconductor (Pocatello, Idaho).