Increases in ASIC design cost and implementation time is opening the door to a new generation of FPGA architectures. These domain-optimized platforms that can meet tough design specifications at a reduced cost, have the flexibility designers need to deal with current and evolving system-on-chip applications. With the help of high-performance silicon cores, designers will be able to use these flexible and low-cost FPGAs to further penetrate the consumer market.
Decreasing ASIC design starts and increases in FPGA design starts over time is a trend that has been well-documented by market analysts. That trend will continue as next-generation platform FPGA devices based on 90-nanometer process design rules expand into more application areas.
Traditional Platform FPGA devices are known for their flexibility, programmable I/O and low overall design cost. But to get the high-performance DSP, processing or connectivity features needed for a specific domain of applications, designers were typically forced to purchase the largest, more costly devices.
For SoC, excessive nonrecurring engineering (NRE) charges and longer time-to-product cycles make it prohibitive for all but the highest volume designs. Furthermore, design risk increases as process geometries shrink, adding additional re-spin mask cost and delaying the device's delivery to market.
Another alternative to standard cell ASICs is a new category of products called structured ASICs. The value proposition for structured ASICs is that they are less expensive and less time-consuming to develop than traditional ASICs with price points matched for midvolume applications. Interestingly, structured ASICs have been compared with FPGAs even though FPGAs have virtually no development cost and require significantly less time to develop.
Now, with shorter product life cycles and increased competition, system vendors realize that getting the product out the door quickly can make all the difference. Hence, the risk of ASIC design for an SoC implementation has become an important concern. An FPGA in place of an ASIC significantly reduces design risk and the cost of redesign if problems crop up since FPGAs, unlike ASICs, can be reconfigured.
The multiple tradeoffs required has lead to a new breed of domain-optimized platform FPGAs that retain the benefits of reconfigurability while providing multidimensional application scaling based on required features and cost goals. Based on a columnar architectural approach, an FPGA vendor can now cost-effectively develop multiple FPGA platforms, each with different combinations of feature sets. Each column represents a silicon subsystem with specific capabilities, such as logic, memory, multigigabit serial I/Os, DSP functions and RISC-based processors.
Reconfigurability is becoming a "must have." First, it provides an inexpensive way to create derivative products. For all but the very largest volume applications, it is more cost-effective to spawn multiple products from a single, reconfigurable platform. Reconfigurability also allows designers to easily adapt to new emerging standards, prevalent in key applications such as wireless and high-speed serial interfaces.
FPGAs also offer the ability to remotely update hardware already deployed in the field. These "field upgradable" systems-such as a cellular base station-can be remotely upgraded with the latest specification and standard in a matter of minutes through the FPGA. Having the ability to remotely update hardware with new features or the latest bug fix can accelerate time-to-market of an application, extend the useful life of existing systems and cut production, maintenance and support costs.
Column-based FPGAs create distinct functional platforms whose mix of base features defines their market domains. Each platform comprises different sized devices with approximately the same feature-set ratio as other devices in the same platform. Each device maps into separate application segments depending on cost and function. This application-mapping process means a single platform device can match a variety of specific applications.
Domain-optimized FPGAs allow multidimensional application scaling through their ability to match both cost parameters and functional feature sets to a wide range of related applications. This simplifies the design of SoCs addressing similar applications within a common domain and the creation of derivative designs from an initial design.
Domain-optimized architectures also simplify the job of designing a chip that best meets the cost and performance requirements of a specific application. This helps the designer in choosing the best architecture, with a more precise functionality, for a particular job.
The features and capabilities of the different domain-optimized platforms are encapsulated within the same basic types of tools and design flow as they did using earlier FPGA devices. The tools "hide" the details of the different IP so that the mainstream designer can do a design without being an expert about the IP microarchitecture. If desired, power users can still go in and manipulate the FPGA to squeeze the last bit of capability out of the design.
Most timing and signal-integrity problems are due to an ASIC's routing. FPGAs do not put these problems into the designer's hands, since their architecture has been designed and verified by the FPGA vendor. Users of domain-optimized FPGAs should not have any increased difficulty in meeting a design's timing specification. If there were problems with a particular implementation, they would be identified early in the design cycle by the FPGA design tools, giving the designer an opportunity to change a device's architecture to better meet performance requirements.
Design-optimized FPGAs give designers a new way to meet the complexity and performance requirements of today's and tomorrow's SoCs. Reduced design cost and time-to-market, coupled with the ability to reconfigure devices to meet changing design objectives, mark this "new breed" of programmable platforms as powerful weapons in the SoC implementation battle.
Chuck Tralka (email@example.com) directs product marketing for Xilinx Inc.'s Advanced Products Division (San Jose, Calif.).
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