Leo K. Wong, Rambus Inc.
Sep 22, 2004 (6:00 AM)
Early work on high-speed serial links (HSSLs) focused on building CMOS components that could generate, receive, and recover timing of high-speed data. This work rapidly improved data rates, however, today's circuits are now running into the bandwidth limitations of the electrical wires as a result. Satisfying the very high symbol rate and very low bit error rate (BER) requirements imposed by today's circuits demands a thorough, quantitative understanding of and compensation for static variances such as dielectric constant, return loss, and inter-symbol interference (ISI) jitter, as well as dynamic variances like temperature and humidity changes.
However, as designers seek to increase the speeds at which these serial links operate, they face another challenge—measurement. In the past, when attempting to improve the performance of an existing backplane channel, the designer would begin by taking measurements of the frequency response, noise characteristics, and transfer function of the channel. The designer would then use the data derived from these measurements to devise and implement a new solution, re-measure the channel and correlate the results.
As data rates approach 3 Gbit/s and beyond, the number of variables for which the designer must account and the enormous complexity involved with isolating and measuring the effects of these variables makes measurement prohibitive both in terms of cost and time. Just consider the typical backplane environment shown in Figure 1 below to understand the severity of the problem.
A Complex Environment
The backplane signal path is a complex environment comprising over 11 different components, each of which has its own variations in electrical characteristics. In addition, there may be up to 10 vias in the signal path, each having both a through and stub component, and each presenting an additional potential impedance discontinuity. Thus, the task of quantifying the range (minimum, maximum and typical) of actual performance characteristics for over 20 components, individually as well as collectively, has become sufficiently prohibitive to suggest using an alternative to measurement—simulation.
Figure 1: Diagram showing a high-speed system backplane channel.
Given the availability of precise models from the manufacturers of the physical components in a backplane channel, and armed with equally accurate models of the serializer/deserializer (serdes) device under development, one might approach upgrading an existing backplane design in a fashion similar to the way a designer would tackle the creation of a new backplane. Once the simulation provides an acceptable BER prediction, implement the design, and correlate the results with actual performance.
There are, however, three key missing ingredients that the designer still needs to make simulation truly effective. The first is a more granular (and therefore more accurate) view of the various components that comprise the effective noise seen by the receiver. The second is a set of algorithms that accurately models the various forms of equalization techniques employed in the design. Finally, having obtained a sufficiently accurate and comprehensive set of models, one must have the ability to gather, analyze, and display the results of the simulation to verify the suitability of the design before implementation. Let's look at each of these in more detail.
1. Modeling Noise
In the past, the demand for essentially error-free operation induced designers to use peak-to-peak noise values to estimate their voltage and timing budget when running link performance analyses. If the designer could show that even with worst-case voltage and timing noise the link "eye" was still large enough, the design was sure to overcome the true statistical noise. However, as designs entered multi-gigabit speeds and ISI started to become a major concern, these methods proved too pessimistic, making the resulting circuit designs either impossible or too expensive to implement in terms of power/area costs.
A similar mistake has been made concerning the nature of the most prevalent and influential type of noise encountered in serial links—deterministic noise. Designers have traditionally and erroneously assumed that all noise sources and ISI in a link are Gaussian and unbounded in nature. Thus, by using Gaussian distribution to estimate the BER of a channel, their predictions have also been overly pessimistic, since most of the noise sources in the link are deterministic, and therefore bounded.
Clearly, designers need models that reflect a more accurate assessment of the nature and impact of each noise component in the system.
2. Modeling Equalization Techniques
To date, link designers have had little to choose from in the way of modeling methodologies that can provide accurate BER predictions for a given HSSL design. Traditional SPICE models are little more than I/O drivers, offering no support for modeling silicon or equalization methods.
A new methodology released just this year called StatEye purports to provide compliance testing of differential channels. According to the developers of the methodology, StatEye models ISI and jitter (deterministic jitter [DJ] and random jitter [RJ]) across a communications link for which the user has selected or parameterized models for each transmitter, receiver and channel function. StatEye also models the electrostatic discharge (ESD), pad, and package parasitics, crosstalk, linear emphasis schemes, and non-linear functions such as equalizers and diode-type coupling components.
Although certainly an improvement over the simplistic legacy channel compliancy models that preceded it, StatEye offers no support for modeling clock and data recovery (CDR), nor for any of the sophisticated equalization algorithms that are essential to HSSL design. Moreover, since StatEye does not provide support for incorporating silicon device models, one would be hard-pressed to maintain accurate correlation between simulated and actual implemented links.
Armed with a comprehensive set of accurate models — of the channel, the device, the noise and the equalization methods — all one needs to complete the task is a statistical analysis of the simulation. The resulting data would enable the designer to assess the performance of the design in terms of BER, offset margins, and link eye characteristics.
Recognizing the need for a more comprehensive set of modeling resources to improve the accuracy of HSSL simulations, a simulation/statistical analysis tool (Figure 2) has been developed that vendor-supplied models for all of the static components in the link (i.e., connectors, traces, PCBs, sockets, vias, packages), accurate noise models, a library of device models, and a comprehensive library of equalization algorithms. These algorithms include including multi-level signaling, partial-response decision feedback equalization (prDFE), and adaptive equalization.
Figure 2: diagram showing the flow chart of the proposed simulation/statistical analysis tool.
The output of analysis tool provides the user with critical system design and verification data that allows an accurate assessment of the performance characteristics of the link. Among these outputs is a cross talk analysis chart.
In the example below, let's consider a legacy backplane with a maximum trace of 46 inches and a target data rate of 5 Gbit/s. We'll use the simulation/stat tool to analyze the viability of a serdes equipped with a 20-tap continuous equalization technology to link this channel.
Figure 2 illustrates the frequency response of the channel under test (victim line in blue) relative to the near-end cross talk aggressor (red) and far-end cross talk aggressor (green). At the target data rate of non-return-to-zero (NRZ) 5 Gbit/s, the Nyquist frequency is 2.5 GHz (noted by red dots).
At 2.5 GHz, the victim line has a 20-dB margin compared to the near-end (NEXT) and far-end crosstalk (FEXT) aggressor. At first glance, one might conclude that the channel has sufficient margin. However, since crosstalk and other channel impairments are additive, one must also investigate other issues such as power noise, reflection and equalization technologies. Therefore, it is necessary to analyze the link margin analysis as shown in Figures 3 to 5.
Figure 3: At 2.5 GHz Nyquist frequency, crosstalk analysis shows that the victim line has a 20dB margin over NEXT and FEXT aggressor.
Figure 4: Diagram illustrating the degrees of attenuation, dispersion, and reflection without equalization.
Figure 5:Diagram showing equalized single-bit response. While the signal is attenuated, DFE removed most of the dispersion and reflection.
Figures 4 and 5 illustrate the single-bit response (SBR) of the channel before and after equalization. Comparing the two diagrams illustrates how a sophisticated 20-tap DFE can overcome channel impairments.
Before equalization, the signal is attenuated by approximately 50 percent, is dispersed across multiple symbol times pre- and post-cursor, and is reflected due to an impedance mismatch in the channel. After equalization, the signal is attenuated by 65 percent. Note that the dispersion (primarily due to ISI) is removed and reflection is minimized. The resulting BER is dramatically improved (Figure 6 and 7).
Figure 6: Diagram showing BER vs. timing.
Figure 7: Diagram showing BER vs. voltage.
Figures 6 and 7 are the "bathtub curves" that plot BER against timing and voltage margins. At a 10-12 target error rate, the signal has an approximate 0.2UI eye opening and 50-mV margin. Based on this analysis, a designer would conclude that this 20-tap equalization, 5-Gbit/s NRZ serdes offers sufficient signal integrity for this channel. Finally, the designer would take into account other considerations such as power, cost, and area to determine the appropriate serdes technology.
The future of backplane design promises more complexity and more innovation. Designers building new backplanes will need to accumulate a continuously growing collection of W-element and component models to extract the optimum performance for their design. For legacy systems, however, one might imagine the facility to automatically gather the channel component models, simulate and analyze the performance of the channel, and introduce the appropriate equalization to meet the target performance, power and cost parameters.
About the Author
Leo Wong runs 10 Gbit and communication product planning and market development at Rambus. Previously, he held senior management positions with BitBlitz and Altera Corp. Leo holds degrees in electrical engineering and computer science from UC Berkeley and can be reached at email@example.com.