Display Stream Compression (DSC 1.2) Encoder
Configurable controllers for PCIe 2.0/1.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
Up to 105 dB of SNR, 24-bit stereo CODEC with PDM to PWM transmodulator DAC and embedded regulator
High performance, energy efficient 4-issue, 16-mac vector DSP core targeted for 4G/5G wireless terminal and Infrastructure applications with scalable vector processing based on the fourth generation ZSP architecture
Innosilicon IP helps Ingenic T20 win "China Chip" Excellent Market Performance Product Award
Appear TV introduces Zero-latency intoPIX JPEG XS technology in the X Platform
Hardent and PLC2 Announce New IP Partnership to Support German Semiconductor Companies
Why a True Hardware PUF is more Reliable as RoT
Antenna Effect in 16nm Technology Node
Analog and Power Management Trends in ASIC and SoC Designs
Talking Sense with Moortec... Staying on the right side in worst case conditions - Performance (Part 2)
Chris Wade maps out UltraSoC's development
A parting view from the Chair: Alberto Sangiovanni-Vincentelli
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