Tim Daniels looks at how one manufacturer’s IP options are designed simplify matching Platform ASICs with the design specification
The sweet spot for Platform ASICs is when the volume costs of FPGA are excessive or when performance/density is important, but the high fixed costs of a full cell-based ASIC cannot be justified (fig 1).
Gartner Dataquest defines “Platform ASICs” as products where up to half the die is predetermined, pre-verified intellectual property (IP), leaving the customer to customise (program) only a portion of it. By far the most popular Platform ASIC type is the embedded array, where the critical IP functions are pre-designed leaving the customer to configure memory and customisable logic via final metal layers. But what IP should be pre-designed and how can the customisable logic produce maximum performance without extensive design time?
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