Infrastructure IPs build ICs out well

While the doubling of transistors every couple of years has enabled the packing of myriad functionalities in a single chip, the challenge now is to bring up working silicon quickly in order to be able to start volume production. This requires the ability to understand, analyze and fix failures in a short period of time, especially with constraints such as higher costs for tester time and designs with tens of millions of devices with limited pin access for debug. Testing is further compounded by complex intellectual property (IP) with limited external access. A new class of IP called infrastructure IP (IIP) is emerging that is embedded in the device. Its sole purpose is to provide access to various IP for test/debug, analysis and yield improvement.

Test challenges

Aside from the difficulty of testing hundreds of millions of transistors, when sub-blocks of the design are populated with IP, many of which are from third-party vendors, there is also a lack of detailed knowledge of the IP blocks, which constrains optimal manufacturing. The lack of access to internal nodes and the "black-box" aspect of many IPs impact the quality and lengthen the time to ramp up production. Also, newer packaging techniques such as BGA make it difficult to probe.

It is predicted that the cost of test may exceed the cost of fabrication unless newer techniques are developed to improve manufacturability of complex systems-on-chip (SoCs). Moving to 90 and 65 nanometers poses other challenges such as longer process maturity time, higher defect densities leading to reduced process yield and more defect types needing higher-quality test algorithms to improve coverage. Consequently, chip realization flow starts at the design stage and continues through multiple phases such as fabrication, debug, volume production, failure analysis and field repair.

Infrastructure IP

Without enhanced detection, test, diagnosis and yield optimization, existing external automatic test equipment (ATE) is insufficient to handle test and yield optimization of large and complex SoCs. Emerging solutions focus on embedding special logic on-chip to test, collect data and monitor signals, and to be able to repair the chip based on analysis the on-chip test provides. These special logic blocks can be developed as intellectual property and embedded into an SoC to enable test and manufacturing engineers to quickly bring up silicon and prepare for production.

Traditional approaches depended on on-chip stored functional test for manufacturing and field tests. However, the size and complexity of today's SoCs have made these approaches almost obsolete, because they are specific to each device and provide only a limited value in silicon bring-up and diagnosis. Instead, more and more designers are turning to embedding IIP in their SoC design to provide direct monitoring and control of various functional blocks.

Examples of such IIP include built-in self-test (BIST) for logic and memories; built-in repair analysis (BIRA); built-in self-repair; error-correcting codes for embedded memories; embedded core test logic for SoCs; embedded timing analyzers to measure timing specifications; and embedded fuse technology for on-chip repair.

BIST involves embedding IP in the design to automatically generate a test and verify the design against manufacturing defects, thus completely avoiding external test generation. The deployment of BIST technology enables a drastic reduction in the test data volume and test time, significantly impacting manufacturing costs. With the extension of the widely adopted scan-based methodology to debug and diagnose, embedded debug IP modules create access to internal scan chains and other control circuitry. The debug IP modules increase the internal observability, allowing designers to quickly localize the errors and enable faster silicon bring-up.

Today, as foundries bring up new processes, volume production begins even before they achieve the defect densities and yield level for that stage. To optimize the design and possibly modify the process to obtain better yield, foundries should diagnose yield problems early in the manufacturing process. Again, infrastructure IP embedded on-chip can be used to collect information needed for yield improvement.

This information, which is related to specific device attributes, is used in the analysis and modification of capabilities to optimize yield. As the technology scales to smaller feature sizes, timing measurement becomes a critical issue. Physical probing becomes extremely difficult at such small geometries, and signal integrity issues can arise as well. With the increase in clock rates, embedded timing analyzers can help diagnose timing-related problems at various stages of the design and manufacturing process.

IIP for embedded memories
The newer processes enable more embedded memory to be packed into silicon, making memories a dominant component of SoCs. Embedded memories are designed with rules that are more aggressive than those for the logic on the chip, so memory defect densities are typically twice that of logic.

Increasing time-to-market pressures often force semiconductor foundries to begin production even before the processes mature and defect densities and yield levels reach a stable state. Hence, yield management becomes an important issue during the early stages of the semiconductor manufacturing process. It involves monitoring and collecting the information on specific device attributes — for example, saturation drain current and temperature coefficients — needed for yield optimization. This requires embedded diagnostic circuits to monitor the various parameters.

One way to manage yield in embedded memories is to use redundant elements during manufacturing repair. Historically, embedded memories have been self-testable but not repairable. Recently, embedded memories, like standalone memories, have been forced to use redundancy because of higher defect densities. Determining the adequate amount and appropriate type of redundant elements for a given memory requires both memory design knowledge and failure history information for the process node under consideration. This alone is a challenge, but providing the right redundant elements does not entirely solve the problem. Knowing how to detect and locate memory defects and allocate redundant elements requires manufacturing knowledge of defect distribution.

Traditional approaches to memory test and repair depended on external memory testers and general-purpose redundancy allocation software to repair the memories. However, the soaring cost of test has given rise to the development of integrated test and repair structures embedded into the SoC. Advanced test and repair systems for memories are usually embedded on-chip to diagnose failed memory bits and repair the failed memory in real-time using the redundant resources (row or columns or both) in the memory. Such a system comprises a test and repair processor along with wrappers (embedding critical test functions) to interface with the memories, a fuse box to store memory reconfiguration signature and the memories (redundant and nonredundant memories) themselves. The processor can have a BIST engine to create memory-specific test patterns; a BIST diagnostic engine to analyze and identify the failure; BIRA; and columns to be topologically efficient post-repair.

Advanced memory test and repair systems employ multiple approaches to repair the embedded memories and achieve optimal manufacturing yield. The embedded test and repair processor, an IIP, interacts with the embedded memories autonomously to test and diagnose each memory and determine whether it is repairable and if so, generate a repair signature.

After the logic tester initiates the test and repair operation, the processor takes over and performs the test, diagnosis and repair signature generation. The tester transfers the repair signature to laser fuse blow equipment, which in turns blows the fuses in the fuse box.

The contents of the fuse box correspond to the repair signature loaded into the corresponding memory for repair by the processor. After repair, the processor retests the memory. Thus the IIP has drastically reduced test costs and minimized external test resource requirements. Additionally, manufacturing costs can be reduced by using nonvolatile fuses, which do not require external laser fuse-blowing equipment. IIP enables multiple time repairs. Consequently, it is useful for field-level repair, especially where nanometer technologies make devices more susceptible to post-manufacturing reliability failures.

As designs become increasingly memory-intensive, with a single design having hundreds of memory instances, it is not feasible to use a single processor to test and repair all the memories. It requires an advanced embedded IP solution with multiple processors to support debug, diagnosis and field repair. A composite IP (a mixture of functional and infrastructure IPs) can have two memory test and repair processor instances. The multiple test and repair processor instances would be connected to each other and to the chip's IEEE 1149.1 JTAG port to provide access to the chip for external test equipment for diagnosis and debugging. Each processor instance can communicate to the JTAG port using a standard P1500 port, a proposed IEEE standard that defines test interface protocol to IPs.

Yield optimization using the infrastructure IP depends on several factors including the type and number of redundant elements, fault detection and localization algorithm, redundancy allocation algorithm, repair strategy and reconfiguration mechanism. Each has an impact on the infrastructure IP's repair efficiency and ability to perform effective failure analysis.

When the functional IP and the infrastructure IP are created by different designers, the boundary conditions between the two, with respect to the factors mentioned above, may be difficult to match. Hence, to increase this impact and maximize yield, the memory IP provider must use the embedded-memory design and manufacturing knowledge base to select those factors in designing the infrastructure IP.

IIP in action
Agere Systems Inc., a market and technology leader for network processors, enhanced the yield and improved time-to-manufacture on the APP550 — a next-generation, edge/access and multiservice network processor, taking advantage of the embedded-memory test and repair infrastructure IP of Virage Logic's Star Memory System. The APP550 is a standalone network processor that delivers wire-speed processing to advanced terabit digital subscriber line access multiplexers, routers, wireless basestations and other communications networking equipment.

High-quality testing to cover all memory defect types was needed to successfully manufacture multimegabit embedded memories in Agere's APP550 network processor.

Agere's yield targets required an integrated, silicon-proven embedded-memory test-and-repair solution to cost-effectively manufacture its APP550 network processor.

The APP550, with a total of 17.8 Mbits of embedded SRAM, used 13 redundant (Star) memory instances grouped into infrastructure IP configuration, each IIP having its own test and repair (Star) processor. The Star memory utilized 25 percent of the total chip area.

The APP550 employed a memory strategy of soft repair on the prototypes. Each of the Star Memory System IIP blocks was tested upon system power-up. The process determined the presence of any memory bit errors and performed repairs using redundant memory rows and columns. In the end, the process successfully increased the manufacturing yield for the APP550, improved time-to-manufacture and significantly lowered per-unit costs.

In fact, using the Star Memory System provided Agere with a 250 percent increase in functional memory yield for the APP550. The traffic-management chip benefited from increased manufacturing yield driven by the tight integration of the memory test and repair IP system (Star) to the manufacturing and test flow.

As the APP550 example demonstrates, the design complexity and rapidly shrinking geometries in today's designs require more than the traditional approach to the management of manufacturing yield. Emerging use of infrastructure IPs for various manufacturing-related functions such as debug, diagnosis and on-chip monitors show signs of reduction in overall test costs and improvement in overall chip yield. End users need more than functional IP, they need embedded IIPs that ensure manufacturability.

R. Chandramouli (r.mouli@viragelogic.com) is director of SMS marketing and Yervant Zorian (yervant.zorian@viragelogic.com) is vice president and chief scientist at Virage Logic Inc. (Fremont, Calif.).

See related chart