The functionality of embedded systems is becoming more and more sophisticated, and their real-time operation makes the debugging and verification of such systems extremely difficult to do in a reasonable time. Some hardware features of embedded processors are dedicated to verification. For example, emulation systems for MIPS and ARM cores allow the user to set breakpoints or read/write registers. However, additional hardware features that we generally designate as embedded test can be made available to verification engineers to accelerate their work.
Embedded test is used in an increasing number of semiconductor circuits to provide a thorough manufacturing test. It is possible to design the test circuitry such that the same high-quality manufacturing test can be reused in a fully or partially configured system. Being able to reuse the original manufacturing test offers a number of benefits to the system verification team. It lets them determine if the circuits are structurally sound. Some latent defects might not be detected at manufacturing time. If a system malfunctions, running embedded test quickly determines whether a hardware defect is the cause. Software developers can spend time debugging software problems rather than trying to debug problems caused by defective hardware.
Latent defects can be due to electromigration, circuit oxide breakdown, hot-electron effect, die metallization corrosion, resistive bridges and negative-bias temperature instability. Those defects are becoming more likely due to process technology changes (low-k dielectrics, small transistors) and the reduced effectiveness of reliability-screening methods such as background current (Iddq) testing, voltage stress testing and burn-in. Each generation of semiconductor circuit sees its Iddq increase such that it becomes more difficult to measure. Voltage stress tests have reduced margins and burn-in is too costly for most applications.
Another benefit of reusing embedded test is that the tests can be run under specific system conditions and point to system design marginalities that could not be detected at silicon-manufacturing time. For example, adjacent circuits might induce more noise than anticipated and cause intermittent system failures or cause the system to work more slowly than expected. Temperature, power supply (e.g., insufficient decoupling, missing branch connections, etc.) and and even cosmic radiation are additional environmental factors that could affect the system timing. Embedded test allows detection and location of these less predictable issues.
Embedded test allows detection of timing issues when designed to replicate the system timing as closely as possible using system clocks instead of separate (usually low-speed) test clocks. Diagnosis is simplified due to the natural partitioning of embedded test. Logic, memory, cores, phase-locked loop, I/Os and interconnect are all tested separately to provide optimal diagnostic resolution. Timing parameters such as a PLL's lock range, lock time, loop gain and jitter can be measured accurately in-system to diagnose high bit error rates. Recent results in measuring on-chip digital jitter indicate that the technology is applicable to signals toggling at gigahertz rates, which are becoming prevalent in modern systems.
Another feature of embedded test, known as fault insertion, allows software groups to verify that faults within a system actually invoke the correct recovery and diagnosis routines. Software typically relies on hardware to detect failures, and based on flags set by hardware, will invoke the appropriate routines. Fault insertion verifies that the hardware is raising the correct flags that the system will actually recover.
Although the behavior of the system under fault conditions is considered during system design, there might be some side effects of the fault that cannot be anticipated. For example, the designer could have assumed in his or her circuit that a dead clock would be stuck low and might not raise the flag when the clock is actually stuck high, possibly leaving the system hanging. Faults can be inserted using the boundary-scan component of the embedded-test infrastructure at circuit pins or any other internal critical signal.
Diagnosing hardware defects from within software is nearly impossible. By providing access to hardware-based embedded-test capabilities, software has access to the fault-detection capabilities that are targeted at finding hardware defects. This access can be provided via the 1149.1 standard interface also used for the emulation systems alluded to previously.
Time constraints can restrict the amount of testing software can perform before the system must become operational. This typically limits testing to a basic memory test and checks to ensure that the processor can read and write selected registers in each integrated circuit. This approach increases the risk of a board failing when it is in service because a defect is not detected until the functional operation of the board exercises the defect. The fast execution time of embedded test can be exploited as part of a board or system's power-up testing strategy.
Embedded test has been used successfully in several systems, such as telecom applications, computers and consumer electronics. It has saved weeks or even months of both hardware and software verification time, depending on the system's complexity and number of embedded-test features implemented. Reusing embedded test for system verification provides an additional return on the silicon investment made to implement embedded test. Thus, it is gaining in popularity for the manufacture of complex devices.
Benoit Nadeau-Dostie (firstname.lastname@example.org) is chief scientist at LogicVision Inc. (San Jose, Calif.).