OCP-based Memory Controller IP Offers Optimal Power and Performance Requirements for 3G Applications

By Michael McKeon, Director, Strategic Products, Denali Software, Austin, Texas

New 3G applications present very unique challenges for memory system designers. There is a need within the industry to process increasing amounts of audio and video data, all from multiple clients, in the system. 3G devices now have the need for mass storage with significant performance, and at the same time, these systems must consume very little power. The change from a simple Flash based memory system to a DDR-SDRAM based system represents challenges on its own. If you take the very stringent power requirements along with the time-to-market pressures unique to the consumer market, and then consider that the memory system has little differentiating value for the end product, you have the perfect case for acquiring intellectual property (IP) for the solution. Third-party IP has emerged as a way for 3G system designers to meet their design and market challenges and focus resources on areas of their core competencies that offer differentiated value in the end system.

Whether designed in-house or acquired in the form of third-party IP, there are a number of options for achieving the power and performance requirements for 3G memory system designs. One key element of the solution lies in the memory devices themselves. Standard DDR memory devices offer some power saving features, like self-refresh modes, but still consume too much power for most mobile applications. Fortunately, key memory vendors such as Samsung, Micron, Infineon and Elpida are developing specialized memories, like Mobile DRAM, that deliver the performance of DDR devices while incorporating power saving modes and functionality for 3G type applications. But nothing is free, and there is always a trade-off to be made. Utilizing the advanced powersaving modes of these specialized DDR devices requires the designer to build more intelligence into the memory controller logic. The cost for using these features is that the designer must design additional logic into the controller to track and maintain information about the critical arrays in each device, and know when to put the memory device into one of the many power saving modes. Another key issue is that the clocking for these new mobile devices does not include the power-hungry DLL (Delay Locked Loop) found in typical DDR devices. In a standard DDR device, the purpose of the DLL is to constrain the data output timing with respect to the clock of the DRAM, thus reducing the skews in the system. Lacking the DLL, these new low-power devices exhibit a much broader skew in the data timing relative to the DRAM clock. In turn, this adds significant complexity to the read capture logic that has to be developed by the memory controller designer.

This drives the need for DLL circuits to reside in the memory controller itself. In the past, DLLs came in the form of power-hungry hard macros architected for much higher frequencies. Unfortunately, these macros and their architecture are simply unusable for low-power designs. Now the designer must come up with a new architecture and design for the DLL function that uses much less power, but retains the functionality and timing to satisfy the DDR send and capture requirements in the 3G system.

To conserve power, memory controller designers also have to control the gating of clocks to the memories and to the controller itself. It is clear that the additional logic for managing the various power modes and additional features for low-power memory devices is a complex requirement in memory controller design for 3G applications. In general, the three main sources of power consumption include: the power consumed by the memory devices, power consumed by the clock activity and power consumed by the DDR controller logic itself. Achieving an optimally low-power memory system requires a memory controller design, or IP core, that addresses all of these issues.

As the leading provider of memory controller cores for DDR-based memory systems, Denali has supported a wide variety of system-level interfaces to its Databahn™ IP product. In particular, customers using Databahn with interconnects based on the OCP protocol, such as Sonics’ SMART Interconnect IP™, gain a very robust infrastructure for the on-chip communication subsystem with the following key advantages:

• Split transaction bus for pipelining multiple read requests
• Separate command and data channels to enhance throughput
• Burst oriented transactions for packetized operations and pre-fetching

These features are significant in that they enable Denali’s Databahn controllers to intelligently transition between the various power saving modes based on interface transaction activity. The OCPbased interface also enables intelligent choices for increasing performance by looking ahead at transaction requests (e.g. utilizing idle cycles for bank manipulations, preparing for other transactions, etc). Databahn also takes advantage of the burst information from the OCP specification to do speculative prefetches. This feature limits exposure to wasted prefetch transaction by regulating transaction size—a programmable feature—and efficiently interrupting transactions. It also reduces overhead for speculative writes by delaying commit to the last possible cycle. In-process writes that need to be curtailed are masked out.

Ideally, the memory controller would incorporate a scheme for automatically transitioning into various levels of power saving modes depending on the activity of the system. The combination of the OCP-based SMART Interconnect IP and Databahn memory controllers provide a significant advantage to SoC designers which address key low-power design requirements in terms of configurability and performance. For instance, the memory controller may contain logic that automatically puts the memory into an initial power down model after around 50 cycles of inactivity. If the inactivity continues for another 100 cycles, the controller might transition the memory into power down mode and shut off the clock to the memory, which saves even more power. Another 1,000 cycles of inactivity might force the memory into self-refresh mode, or partial array self-refresh mode. This scheme of progressively reducing the power consumption would continue for n modes, ultimately resulting in modes where the controller places the memory in the minimum power consumption state, and then the controller itself would shut off all non-critical clocks and simply monitor the system interface for any potential wakeup activity.

The memory controller might implement a simple scheme to automatically reduce power consumption from the controller and the memory devices in a series of stages as follows:

• Mode 0: Normal operation – no power saving modes activated.
• Mode 1: Memory is put in power-down mode and is only reactivated when a refresh is required.
• Mode 2: Memory is placed in power-down mode and the clock to the memory is gated. Once a refresh is issued, the memory is returned to power-down mode and the clock is again gated off.
• Mode 3: The memory is placed into self-refresh mode and the controller does not actively issue any commands. In this mode, additional logic can be used to control partial array refresh for additional power savings.
• Mode 4: The memory is placed into self-refresh mode and the clock to memory is gated off.
• Mode 5: Maximum power saving mode. The memory is placed in self-refresh and the memory clocks are gated off. In addition, certain nonessential portions of the memory controller are turned-off.

In addition to automatically controlling power modes, the controller must also provide a mechanism to enable software or firmware designers to force the memory system into any particular mode based on the anticipated activity in the system. For example, when the 3G application senses an upcoming request, such as video data, the software might query the memory controller for the current state and optionally force it into the optimal mode for processing the upcoming data requests. This is necessary since it could take thousands of cycles to wake-up the memory system from a deep power down mode. Alternatively, the system could skip the automatic progression through the power-down states initiated by the controller and initiate maximum power savings based on other system-level information.

While memory vendors are providing new memory devices to address the unique need for power and performance in 3G applications, it is clear that designers are faced with a very challenging set of requirements for designing the associated memor y systems. From a technical perspective, the move from Flash or SDR AM-based designs to DDR systems is a significant challenge on its own. The added requirement for extracting higher performance from these new devices, while simult aneously managing power states, requires significant expertise and resources. Denali’s native multi-port Databahn controller cores, combined with the OCP architecture, offers a robust multi -threaded solution for optimal per formance and intelligent power management in a multi-client system talking to shared DRAM resources—the perfect solution for 3G applications.