The semiconductor industry is expected to provide complete and optimal system solutions, including silicon, firmware, external components, board layout (in the form of Gerber files) and even, in some cases, man-machine interface software. These highly integrated systems-on-chip, particularly wireless SoC devices, require developers to pay considerable attention to optimizing trade-offs among cost, power consumption, size, performance and scalability. But achieving the right balance and associated integration level is a moving target.
Memory dominates today's SoC real estate; DSPs and RISC processors consume very little space by comparison. Yet, ironically, far more effort is often expended in optimizing the DSP and RISC processor.
Deciding on the most appropriate on-chip memory strategy can generally be accomplished early on, based on application needs, cost sensitivity, software maturity and so on. Selecting the memory size will be based on best estimates of code/data storage needs plus a degree of headroom. For example, if a large protocol stack is involved but has not yet been developed, the degree of headroom required can be as much as double your initial program memory estimates.
On-chip, ROM-based program memory offers an alternative to low-cost systems-on-chip, but it comes at a price, since in-field upgrades cannot be supported. Even in cases where code is mature and bug-free, many applications require support for in-field product feature enhancements and thus require reprogrammability.
As program and data memory sizes grow, it becomes economic to employ on-chip cache with slower (and therefore lower-cost) external memory. Using data compression or real-time compiling techniques can also permit reduced program/data memory needs.
Many DSPs now have RISC capability and thus can efficiently perform data management in addition to their traditional, signal-processing workload. It is therefore feasible to implement voice and lower-complexity audio solutions using a single DSP and no RISC processor. As the signal-processing load increases, however, it is common practice to include a RISC processor and reassign the protocol to free up DSP Mips for that additional workload.
For even higher-signal-processing tasks, such as high-definition MPEG-4 or even standard-definition H.264 video processing, it may be necessary to include a dedicated coprocessor in addition to the DSP and RISC processors. Allowing for the nominal increase in die size, many signal-processing tasks can be more efficiently accomplished using dedicated coprocessors. The system clock can run slower with coprocessors, thus saving power.
The ultimate challenge today lies in the integration of the RF transceiver into an SoC. The only technology that is economically viable for supporting such integration is RF CMOS.
Although this process can offer significant cost advantages over alternative, more linear processes such as SiGe or GaAs, additional layers (not required for digital CMOS circuits) still exist. As a result, integrating the radio into an SoC will increase the baseband implementation cost compared with using digital CMOS. In most SoCs today, the digital circuits cover more than two-thirds of the chip.
Moving to smaller-geometry CMOS offers area reduction and therefore cost savings for the baseband (digital) circuits. Traditional radio architectures, however, tend to be dominated by analog circuits, which do not scale as well.
Reduced geometries also mean reduced supply voltages, limiting the dynamic range available for analog signals and thus rendering the radio more susceptible to noise. There are a lot of potential noise sources on today's SoCs; many I/O circuits operate in the 6- to 10-GHz range, and some reach as high as 40 GHz.
By undersampling (relative to the Nyquist sampling frequency) at the low-noise amplifier output, it is possible to achieve similar results to traditional analog mixers. Meeting even Bluetooth's spurious-free dynamic range, however, would require a rather large (16-bit) sigma-delta A/D converter and a 16-bit digital finite impulse response or infinite impulse response filter. Aside from its size, such a circuit (including the sampler) represents challenges to offering low power consumption.
If the digital filter is implemented using capacitors to store each tap result as a charge, then the digital circuit size and resulting power consumption can be reduced. This approach is dependent on very low-leakage capacitors and is also vulnerable to RF noise, in the same manner as traditional radios.
In order to develop a successful analog/RF IC, the design engineer must have more design support from the foundry. In fact, because of market growth of RF/wireless applications, most design companies are choosing foundry service based on the quality of the foundry's analog/RF design support.
When it comes to RF CMOS IC design, many hidden effects, in particular parasitic effects, tend to be modeled in the design flow. To avoid these complex design challenges, United Microelectronics Corp. is working with EDA vendors to provide foundry design kits for each process generation. In the FDK, the circuit descriptions for simulation closely resemble the layout by the parametric cell; for example, the drain/source area in the simulation netlist can exactly match the layout.
To model the device operating at gigahertz frequencies, a subcircuit block is used. A set of spiral inductor libraries or either metal-insulator-metal or metal-oxide-metal capacitors is built in the FDK. With this, the layout and an electrical model can be generated.
Design flow example
Designers continue to be under tremendous pressure to achieve designs that meet the criteria of "right the first time" even as development cycles shrink. While it is tempting to jump into crafting hardware, for high-complexity designs it is generally prudent to invest up front in a high-level software model. Such a model will support functional validation early in the design cycle. Other advantages include early functional simulation and debugging of firmware, as well as later co-simulation for hardware verification.
Different design methodologies can be used for each functional unit. For example, SystemC can be used as simulation for the WLAN MAC high-level validation. WLAN reference SDL can be modeled using SystemC early in the design cycle and then converted to a hardware block once the overall hardware/software partition is determined.
After high-level system validation using SystemC, the hardware can be implemented in VHDL, while the software can initially be implemented on an FPGA-based prototype board for functional verification before hardware is completed.
Since the complexity associated with validatrion makes it unrealistic to integrate all of the intellectual property into a single FPGA prototype board, it's best to settle for verifying each IP block in a reduced platform. Such a platform might include the embedded processor, system bus and tested IP itself.
James Benefer (email@example.com) is director of technical marketing for GCT Semiconductor Inc. (San Jose, Calif.).
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