Process Improvements for System on Chip developments

The development of system-on-chip products requires some rethinking of the development process. The SoC designs for transport silicon for the telecommunications market carry with them a new degree of complexity that can stretch traditional chip development techniques to the breaking point. The telecom market segment also has been in flux to a great degree, so network equipment is evolving at a high rate of speed. This market turmoil creates a challenging environment for SoC teams, which must not only track the changes but often anticipate them as well.

In the specific example of our add/drop multiplexer-on-chip (AoC), the original version went straight into production and required no metal-mask changes. While this was an exceptional accomplishment, based on the evolving needs of the telecom market, we realized that we still needed to make a fundamental improvement in our ability to bring products to market. This resulted in the establishment of the breakthrough goal of six months from spec to tape for design variations of our SoC family.

Importantly, undertaking the highly complex AoC project in the United States in the face of outsourcing pressure from the investment community required that we make significant improvements in our processes in order to remain competitive. Indeed, we and our investors discussed locating a design team overseas in order to remove cost from the process. In evaluating this option we took many things into consideration such as the cost and availability of engineering talent, proximity of the design team to the markets we serve, the communication issues that surface with substantial time zone differences and the ability to bring products to market quickly.

Our conclusion at the end of this study was that we would continue to do our design work locally using the best and most experienced team we could build. The swing factors of this decision came down to time-to-market for our products and the need to ensure a high degree of quality over a sophisticated SoC development process. This decision was not without controversy, as the conventional wisdom is that you can save over 50 percent of your development costs by moving offshore.

Our belief in the ability of a seasoned team to consistently create design breakthroughs was a key consideration. That said, however, innovation is not limited to the design function. We believe that there is a substantial advantage to be gained through process innovation as well.

Over the years, the team has developed an analytic process discipline that involves a retrospective view of SoC development. This involves collecting information on individual products and pieces flowing into the development and a postpartum analysis (we prefer this term to post-mortem) to understand how our tools performed and where we spent our time.

A critical learning point for us is that faster time-to-market involves looking at the entire process and not just the design phase. For example, with system-level or SoC products, the verification process becomes a significant part of the overall schedule.

With this in mind we set the following goals:

• Six months from specification to design tapeout for product variations;
• Establish consistent methods and tools to ensure fast design execution with high quality;
• Improve predictability on project schedules;
• Use designs and processes that are transferable to new designers and teams; and
• Achieve faster overall time-to-market.

There are a number of conditions that are assumed to be in force to achieve these goals. The first is that the specification must be frozen, with no substantial changes. Specification turmoil is very destructive to schedules, and one benefit of a quick time-to-market cycle is to reduce one of the sources of specification change — market conditions that change between the time the specification is defined and the time the product is designed. The second is that process techniques are no substitute for projects that are properly staffed with quality engineering talent. And finally, it is essential to create modular designs that enable a high degree of reuse of well-tested and thoroughly characterized modules.

We are approaching these goals with a methodology built on four basic ideas. The first is to establish a common flow for the entire process. Having a well-documented life cycle will enhance our ability to train engineers, and allow for clear and concise communication concerning each stage of the process. The second idea is to automate where possible. There are a variety of tools that can be sourced externally that help in this regard, but others must be developed internally and require budget and resource commitments to ensure development.

The third point, in which the verification process is streamlined, has a high degree of schedule leverage. By streamline we mean two things. First, it is essential to create a consistent, documented and reusable verification environment. Second, it is important to note that verification of an SoC project is largely a software task. Developing software-engineering expertise specifically for verification tool development and verification execution results in a substantial reduction in overall schedule.

The fourth point is to streamline the back-end flow. One of the crucial points for the SoC products in our domain is to improve the clocking methodology to improve clock tree synthesis and minimize or entirely remove manual intervention.

We set the goal of having the six-month spec-to-tape process in place 18 months from the time we began the effort. We started working on improving the process in January, and after six months we believe we are making good progress toward the goal. Having a small team to initially establish and implement the process has been helpful.

A good test of our progress will come over the next few months as we continue to ramp up the engineering team and bring on new employees. We will be looking at how easily they adapt to the process, and how transferable each piece of the methodology is. It will require continued commitment at all levels of management and continued focus on the discipline of process development.

Partha Srinivasan (Partha@paramanet.com) is chief technical officer at Parama Networks Inc. (Santa Clara, Calif.).