RF integration: Changing the face of test

In the wireless world, the only constant is change. With the push for single-chip implementations of wireless products, new radio architectures are emerging. This can be seen in mobile phones, wireless-LAN and Bluetooth applications, and more. In the face of integration, fundamental changes must occur in test to ensure quality product while minimizing test costs.

Test methodology is affected by the availability of access points for test. Today, many radio designs provide the access necessary for parametric testing of the individual blocks. As integration levels increase and access points are reduced, a new test methodology is required.

One example of this can be seen today on simple modulation radios, such as Bluetooth and cordless phones. The most common partitioning includes the RF radio and the signal decoding and encoding functions on a single chip. In place of parametric tests of the individual blocks in the receiver, bit-error-rate (BER) measurements are taken on the receiver under several RF stimulus conditions.

A second example is the emergence of radios designed using digital architectures. This trend will increase the rate of radio integration into systems on-chip and will change the functional blocks used in the radio design. For instance, the traditional demodulator and A/D converter functions may be replaced with a sampled-data converter. These new designs most likely will not support traditional test methods and will increase the dependency on system-level tests.

System-level tests, like BER, not only accommodate an integrated radio architecture with few access points but also provide real-world test conditions to determine the true performance of the radio. This is especially important for today's digitally encoded signals with high peak-to-average ratios, as seen in such wireless standards as Bluetooth, WLAN and cellular. System-level measurements — such as BER, error vector magnitude (EVM) and adjacent channel power ratio (ACPR) — will capture numerous device impairments with a single measurement. These system-level tests identify defects such as poor signal-to-noise ratio (SNR), spurious signals (e.g., local-oscillator leakage, harmonics, intermodulation), phase noise, and I/Q1 imbalance (amplitude and phase), plus crosstalk and isolation of the individual radio blocks. When performed under different stimulus conditions, the radio can be entirely tested with system-level measurements and a few basic power measurements.

System-level test
As new radio architectures emerge, system-level test will be key to ensuring quality product with limited test access points. This trend requires a test system with integrated high-performance digital, analog and RF, in order to support EVM, BER and ACPR measurements of current and emerging wide-dynamic-range modulation formats.

For example, EVM measurements on an IEEE 802.11a/b/g WLAN transceiver require a test system RF receiver with greater than 22-MHz bandwidth and a spurious-free dynamic range (SFDR) greater than 80 dB, as well as high-performance analog.

To support a high-speed interface between the radio and baseband processor devices, such as the proposed Jedec JC-61 standard or PCI-Express, high-speed digital pins (up to 2.5 Gbps) are required on the test system. In general, RF stimulus requirements will go from simple CW2 or single-tone modulation inputs to more complex signals with multiple modulated carriers and CW interference tones, to ensure the same coverage achieved with parametric testing.

Reducing test costs
The integration of a radio into an SoC or SIP creates a complex device for testing. One device will contain logic, embedded memory, high-speed memory interfaces (such as DDR4), mixed-signal blocks like analog to A/D and D/A converters, and now, the RF radio. The test system required will be equally complex with a range of capability.

To maximize efficient use of all test system resources while reducing test times, a methodology in production today for complex mixed-signal devices can be used. Known as concurrent test, it involves testing multiple IP blocks on one device at the same time. For instance, the logic and memory can be tested in parallel with the RF radio. Typically, concurrent test will require special design-for-test considerations in the SoC design phase. The fundamental requirement is that IP blocks on the SoC be isolated so they are independently accessible, observable and controllable.

Another technique for improving throughput and reducing test costs is testing multiple devices simultaneously. When looking at implementing multisite test, the number of test resources required must be examined to determine whether the test system can be configured with all the necessary capability, especially digital pins for test of the processor, embedded memory and DSP.

It is also important to analyze whether or not additional hardware will be required on the DUT board, for example a splitter for the RF stimulus, switches, attenuators and so on. Trade-offs between the cost of adding enough resources to implement multisite test and the throughput improvements that can be achieved must be weighed.

In the end, the test methodology of a highly integrated SoC with RF will depend largely on available test access points and test cost goals. System-level tests, like EVM, BER and ACPR, enable thorough, real-world testing for integrated radio devices with limited access points. Multisite and concurrent test can then be implemented to provide a significant cost-of-test savings for complicated RF SoC devices.

Mandy Davis (mandy_davis@agilent.com) and Gina Bonini (gina_bonini@agilent.com) are product managers on the 93000 SoC Series at Agilent Technologies Inc. (Palo Alto, Calif.)