| As semiconductor manufacturing capability allows designs that integrate tens of millions of gates onto a single device, system-on-chip (SoC) has taken center stage as the IC technology of the future. However, when people talk about SoCs today, they are really talking about only partial systems — about integrating digital baseband gates along with data converters, some high-speed analog IO, and perhaps even some RF — as long as it's not too complicated. |
RF integration is generally acknowledged to be an essentially unanswered SoC challenge because of incompatible process technology. Imposing the yield limitations or high test cost of RF circuitry on high volume digital die can significantly increase production cost.
But the barriers are more varied and subtle than that. RF integration, from the perspective of a SoC system hierarchy, presents some difficult development challenges in circuit design, physical implementation of hardware components, and manufacturing/test.
RF chip designers now have a second option. Recent developments in CMOS manufacturing process technology overcome RF integration barriers by enabling developers to move RF processing into the digital domain. Instead of having to struggle to design and implement analog components, chip designers can employ digital RF techniques to process RF signals using familiar and proven tools and processes.
Bet you can't integrate just one
To fit all of the processing silicon that is required to implement today's advanced features into the small form factor of a handset or PDA requires integration of digital, analog, and RF onto a single device. Otherwise cost and form-factor limitations will stall the deployment of new handset features. Integrated radios consume roughly half the power, half the board space, and half the silicon area of traditional radios. Consequently, radio integration can offer a tremendous benefit in meeting handset design goals.
Consider the data processing requirements of 3G handsets. On the digital side, users expect higher resolution color displays, games needing additional memory and graphics resources, PDA application functions, and multimedia functions such as photography, video conferencing, and audio playback. On the RF side, it isn't unreasonable for a phone to need more than a handful of radios, including the following:
Today, RF components number more than half of the total components on a board and, for a simple radio, occupy up to 40% of a phone printed circuit board (PCB). Adding radios to support such functions as Bluetooth, GPS, and wireless LAN, increases these figures significantly. While radios can share some circuitry, the radios will have to be smaller than they are today if expected to fit within a single device.
- Many GSM phones support a total of four bands — cellular and DCS for Europe, and a different cellular frequency and PCS for the U.S.
- UMTS at 2.1 GHz
- GPS for positioning and synchronization
- Bluetooth for PAN connectivity
- WiFi for network connectivity, can share Bluetooth radio if 2.4 GHz 802.11b/g
- Digital Television
- Digital Audio Broadcast and FM over the air
Problems behind the scenes
The practical issues of integrating digital, analog, and RF circuitry can put a damper on anyone's enthusiasm for total silicon integration. Available EDA development tools still leave much to be desired for the design of sophisticated RF circuitry on an SoC.
Tools for examining digital and RF circuitry at the same time are still in their infancy, never mind for simultaneously validating and testing designs. Other limitations include poor matching of small components, high 1/f noise, and a lack of on-chip passive components (resistors, capacitors, varactors) with adequate analog characters.
Despite these challenges, integration is an essential element of enabling smart phones to reach mass adoption by reducing cost, power, and complexity of radio design. The industry requires significant technology advancement at the wafer process, system design, and circuit design levels to make radio integration a reality. While many SoC technical challenges are of little concern to designers using SoCs, these challenges are important to understand because they define practical device capabilities and limitations. For example, while integrating RF using a bipolar or BiCMOS process is technical feasible, yield limitations and the high cost of testing devices makes it unlikely that any such devices would achieve volume/commercial viability.
Integrating SiGe BiCMOS technologies is also a possibility. However, SiGe technology is typically one or two process nodes behind state-of-art digital CMOS process nodes. Given that handsets are requiring increasingly more digital processing resources, SiGe doesn't keep the more significant digital portion (especially memory) of the die cost at a minimum.
Even CMOS RF integration has its challenges. Implementation of analog mixers, filters, and amplifiers is difficult, especially as voltage levels drop, and device modeling in the early stages of new process nodes is generally inadequate for the highly accurate parametric modeling required for analog block designs. The industry needs a significant design innovation to allow radios to be integrated in standard CMOS and take advantage of the performance of CMOS technology, instead of fighting its limitations.
Digital RF integration
One way of surmounting RF integration issues is to take a different approach that avoids them altogether. This can be accomplished by shifting the functionality of RF components into the digital domain.
By processing RF signals in the CMOS digital domain, complex and expensive analog masks become unnecessary. Chip design also becomes easier because developers have more access to system details during simulation, as well as more control over the processing of a signal by implementing processing as a combination of reprogrammable software and hardware elements.
For example, noise coupled from the power supplied to Tx and Rx voltage controlled oscillators (VCOs) affects overall system efficiency. Regulators and associated passive components are required in most radio board designs to address these issues. Integrating these components into the radio transceiver means that simple decoupling capacitors are the only external components required for direct connect to the battery, both simplifying design and conserving board space.
Designers also have the option of incorporating digital tuning functions and self-calibration into the VCO. This expands the tuning range of the VCO making integration of loop filter components feasible.
In order for digital gates to process analog signals, they must operate at very high speeds. Device transition frequency, Ft, is one easy way to assess process capability for RF signals (see figure 1). Ft is the frequency at which the small signal transistor gain falls to unity.
Figure 1 — Tracking the transition frequency Ft of each process node provides a ballpark estimate of which communications bands can be processed in the digital domain.
A general rule of thumb is that Ft should be roughly ten times the operating frequency. For example, to process 1.9GHz signals, an Ft of roughly 19GHz is needed. Lack of sufficient Ft was a significant limitation for older CMOS processes. However, today's 90nm technology offers Ft performance of more than 100GHz. This very high Ft easily exceeds all requirements for cellular handset radios.
Digital RF processing has been taking place in stages over the last decade. Yet, as SoCs move to the 90nm process node, the meaning of "high frequency" will be redefined as Ft increases. Today, DSPs running at 1 GHz are able to process "high" frequency signals entirely in the digital domain, even using software to dynamically manage processing.
Recently, TI announced the BRF 6150, a second-generation Bluetooth SoC device. This device provides an excellent example of how SoC integration in a CMOS process technology can simplify design while reducing board real estate requirements and system cost. The BRF6150 integrates the Bluetooth baseband, digital RF, and antenna switch in a 4.5mm x 4.5mm package, enabling designers to add Bluetooth functionality in 50 square millimeters (see figure 2).
Figure 2 — BRF 6150 integrates Bluetooth into system-on-chip.
The integrated BRF6150 consumes 30% less power than competing solutions, and only 6uA when in power shut-down mode. A direct battery connection eliminates the need for external regulators, and the device requires only 11 external components, easing design complexity. This integrated Bluetooth device is typical of the end results of increased integration and the move towards true digital radio.
One reason we can integrate Bluetooth today is that it uses a relatively low power signal going only a short distance. Modern handsets require sensitivity on the order of -106dBm, must be able to reject energy in adjacent frequency bands on the order of 60dB, and operate with oscillators that avoid folding phase noise into the receive band. These extreme performance requirements make radio integration a much greater challenge. Many of the key components required to enable designers to meet these stringent design constraints are already finding solutions in the digital realm. Today, for example, fully integrated digital frequency synthesizers are available, with all internal components on-chip and no external pins, an important milestone in RF integration.
Another key advantage of integration is that by designing at smaller processes, radios can run at a lower operating voltage. In most cases, running at a lower voltage is decidedly an advantage, resulting in longer battery life, one of the primary barriers to introducing new features to existing handsets, as well as less heat dissipation.
Low voltage, however, introduces new fundamental problems, such as dynamic range. The dynamic range challenge, for example, is illustrated by the near/far problem of wireless communications. For example, if handset A is close to the cell and handset B is farther away. Handset B has to transmit at maximum power to reach the cell.
While channel A and channel B are on different frequencies, the high power signal of channel B may "leak" into channel A, requiring handset A to reject the far channel interference in order to receive microvoltage signals in the presence of high power transmissions. Fortunately, problems such as dynamic range can be addressed in a straightforward fashion with front-end processing.
The generation of higher power signals that are suitable for driving an antenna is a key challenge in SoC integration. Normally, the high power levels, elevated voltages, and thermal considerations of power amplifiers for wide area networks (WANs) makes them unsuitable for integration in deep submicron CMOS.
However, it's important to note that these problems are primarily relevant to legacy wide area networks (such as GSM and CDMA) Shorter distance personal area networks (PANs) and local area networks (LANs) are amenable to power amplifier integration.
In such SoC designs, close proximity of the power amplifier to data processors allows automatic calibration systems to enhance overall system performance. Additionally, digital RF could accelerate the development of some emerging shorter distance networks which might include UWB, Zigbee, and mesh networks by making available the cost, space, and power savings enabled by RF integration.
Validation in volume
Another key barrier to analog RF integration, perhaps even more daunting than maintaining yields at the high volumes demanded by handsets, is that of validation. Production RF testers typically cannot test arrays of digital logic, nor do logic testers offer analog or RF capabilities. The RF portions of a large SoC cannot be allowed to materially impact overall yield, nor can they slow the migration of an SoC to the latest available process node.
Digital RF processing, by the very act of moving RF functionality into the digital domain, makes the process of testing and validating radios approach that of logic-only devices. While a complete migration will never be possible — some level of analog and mixed-signal functionality must always be present — digital processing techniques can be employed that improve the efficiency and reliability of testing and validation processes.
With digital RF it becomes possible to fully analyze baseband signal characteristics on the SoC itself, and a handful of external analog components enable loop-back tests to reliably assess signal quality. In this way, radio performance can be measured at the system level, as opposed to a functional block level.
Not only does this reduce the number of measurements required, it simplifies certification. SoCs can be designed with self-test capabilities to self-calibrate and reduce the effect of parametric variations on yield, potentially increasing production yield to defect-density limitations while dropping radio test costs to insignificant levels. Additionally, digital RF blocks maintain the capacity to migrate processes, allowing scaling of devices, an important requirement for high volume devices.
Being able to implement RF functionality in the digital domain also reduces cost and complexity by enabling optimization at the system level. For example, handling the many frequencies from multiple radios requires more than just placing multiple radios on the same die. By working at a system level, designers can implement circuitry to mitigate in-band spur generation.
Designers can also develop new architectures that facilitate the hardware sharing (for example, two radios that share a functional block) required to further shrink radio size. And since these new architectures will be implemented primarily in digital logic, developers will be able to use familiar EDA simulation and synthesis tools, as well as digital test and manufacturing test suites.
RF is indisputably the next key challenge of SoC integration. With the continued advancements of manufacturing technologies such as CMOS processes, however, RF processing has already begun the shift to becoming a design issue of the digital domain.
With each process node shrink and increase of transistor speed, digital RF processing can accommodate more and more of the communications spectrum; the existing momentum of digital RF processing will result in a single-chip GSM radio by the end of 2004. RF integration is no longer a question of possibility, and SoC devices can finally become truly complete systems on a single chip.
Bill Krenik manages the Wireless Advanced Architectures area at Texas Instruments. His responsibilities include advanced research and technology development for the future wireless product space. Previously, he has held roles as general manager of the RF Products group and the Analog Mass Storage Products group.
Gene Frantz is one of the country's foremost experts in digital signal processing. In 2002, he was named a TI Principal Fellow, joining an elite group of technology innovators who have achieved the highest rung on the TI technical ladder. As DSP business development manager, Gene is responsible for creating new businesses within TI utilizing digital signal processing technology. Frantz joined TI's consumer products division in 1974, where he took a leadership role in the development of TI's educational products.