With the emergence of such wireless standards as wireless LAN, GPS, Bluetooth, ultrawideband, Zigbee and DVB-Handheld broadband wireless, semiconductor and handset manufacturers are presented with new opportunities. The ability to combine protocols to provide a continuity of experience to the user by extending the network seamlessly can now be achieved. But this opportunity leaves manufacturers to face several formidable challenges.
The first is simply to keep pace with the rate at which new standards are introduced and old ones evolve. The next is to determine which combinations of technology to integrate into a single device. To minimize risk in the selection process, a means for defining the modes of operation after silicon implementation is necessary.
The third major obstacle is seamless interoperability among modes. Here, the software-defined radio concept would seem to be the ideal solution.
SDR must have the flexibility to be controlled and the agility to operate, with modulation independence, in multiple bands and modes. In a cell phone application, a complete SDR consists of all elements from the antenna to the speaker and display on the receive side, and from the microphone and camera to the antenna on the transmit side.
One key element is the transceiver. Specifically, the SDR transceiver would include RF and channel signal processing, providing a baseband digital output on the receive side and accepting a baseband digital input on the transmit side. The critical issues and some techniques to address them deserve close examination.
The SDR concept has been around for several years, but implementations have mainly been limited to military applications or infrastructure solutions, where cost, size and power dissipation are not the greatest concerns. The result is an overdesigned solution in many of the typical modes of operation. But advances in CMOS process technology and increased simulation and modeling capability are narrowing the gap.
The two key hardware design considerations for closing the gap for SDR are moving the data converters as close to the antenna as possible and designing for performance on demand.
Consider the case of a 3G UMTS dual-mode (W-CDMA and GSM) handset as a candidate for SDR. Notwithstanding the fact that wideband code-division multiple access maintains full-duplex operation, this may be as simple as it gets from the perspective of dual-mode operation. Since such handsets operate in licensed frequency spectrum, the interference between users is very well-controlled. The 3GPP standards body controls the specifications for both modes of operation and therefore defines those aspects-such as concurrency, handoffs, authentication and security-that typically cause concerns in multimode operation.
For the Universal Mobile Telecommunications System standard, something as simple as the system clock frequency can become a major issue because each standard has unique system timing requirements. A flexible SDR architecture will require many clock sources, some of which may require very high spectral purity (for data converters and synthesizers) or long-term stability (for maintaining synchronization with the infrastructure equipment).
One of the most significant improvements in the past three years is the integration of low-noise voltage-controlled oscillators in the 2- to 5-GHz frequency range. This improvement, due largely to advances in CMOS technology and RF CMOS design, has revolutionized integrated transceivers. Completely integrated multiband single-mode transceivers have become commonplace.
With the increasing desire to move the data converters closer to the antenna, the converter design becomes tougher. In the example shown above, the modulation bandwidth in the W-CDMA mode is more than 20 times higher than the Global System for Mobile Communications (GSM) requirement. But fewer effective bits are required for W-CDMA, because of the large power control range used.
This is the ideal situation in which sigma-delta A/D converters can be used to provide performance on demand. A 2- or 3-bit sigma-delta A/D operating at roughly 50 MHz, with a programmable decimation filter, can meet both 2G and third-generation needs in a cost- and power-efficient manner.
The emergence of standards with very complex modulation schemes, such as IEEE 802.16e, will add even more complexity to the data converter design, however. To handle this increase in complexity, advances in CMOS process technology enable design improvements for data converters in the areas of calibration, higher sampling rates and high-speed signal processing.
A GSM quadband phone typically requires four LNAs and two mixers. With 130-nanometer and 90-nm CMOS technology, CMOS LNAs and mixers for wireless protocols in the 1- to 5-GHz range are easily achievable. The RF circuit topologies, however, have changed to align more with the capabilities of CMOS. The biggest challenge for RF CMOS design is choosing architectures that minimize the number of pins and the area of passive components.
Power amplifiers have always been treated as a separate entity because of their high power dissipation, high-voltage requirements and low-supply-noise requirements. An SDR power amp, in addition to supporting multiband, multimode operation, must be capable of efficient linear and nonlinear amplification.
Despite the advances being made in CMOS integration and in new system and circuit techniques for the transceiver, challenges remain in minimizing the number of RF switches, receiver selectivity filters, transmitter harmonic filters and antennas for multiband operation. Further, the SDR transceiver must be coupled with a flexible baseband and additional memory storage to support multiple protocols for a multimode phone.
Considerable research still needs to be done to reach the fundamental objective of achieving a high-volume-production multiband, multimode SDR device at 20 to 30 percent cost, size and power-drain performance penalty compared with a single-mode device.
Ken Hansen (Ken.Hansen@freescale.com) is senior technical fellow and Kevin Traylor (EKT011@freescale.com) is fellow of the technical staff at Freescale Semiconductor Inc. (Austin, Texas).
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