Escalating processing requirements for new multimedia functions has forced designers to turn to dual-processor handset architectures that offload much of the multimedia work to a separate applications processor. In addition, the emergence of high-performance handsets capable of supporting not only 3G cellular standards but also higher-speed wireless data interfaces like 802.11 and digital multimedia broadcasting (DMB) are laying the foundation for a new generation of multimode handsets that employ three embedded processors.
While these handsets provide the coverage and compute power required by today's wireless applications, they also introduce a potential performance bottleneck. The data rates associated with these noncellular wireless standards far exceed the performance capability of 3G wireless systems. To reap the maximum utility out of higher-speed wireless interfaces like DMB or 802.11, these handsets must provide an interprocessor communications scheme capable of supporting those data rates.
Complicating the design decision is the fact that any interprocessor communications architecture must also support low operating voltages and consume minimal current to extend battery life. It must use extremely compact packaging to conserve precious board real estate. Finally, to enhance design flexibility and enable the use of a highly modular system architecture, it must employ an interface that is compatible with most major vendors' applications and baseband processors. This will allow design teams to target a variety of geographic regions or market segments with minimal design resources by using the same basic handset design and simply swapping out processors.
Designers managing the communications flow across a multiprocessor handset architecture have three primary options. The first is to use common embedded interfaces such as integrated UARTs, I2C or USB. These embedded interfaces offer a highly compact footprint and help drive down system cost since they require no additional logic. Moreover, they consume little additional power. That said, each has its performance limitations.
At 230 kbits/second, a UART-based interface can support text-messaging and basic 2.5G wireless interfaces such as GPRS. An I2C-based design, at data rates up to 400 kbits/s, will support Edge implementations. But the interface will present a major performance bottleneck for systems running newer cdma2000 3x, W-CDMA or cdma2000 1xEV-DO networks.
Low-speed USB 1.1, which is currently supported by most embedded processors, provides a maximum bandwidth of 1.5 Mbits/s before compensating for overhead and handshaking. But even this additional bandwidth will fall short in high-performance 3G networks. The limitations will become profoundly more apparent when the handset is accessing an 802.11b Wi-Fi network running at 11 Mbits/s or higher.
A second and more practical option, from a performance standpoint, is to use a proprietary approach. Implementing a multiprocessor communications scheme using a custom ASIC or a proprietary bus such as those offered by some embedded-processor manufacturers offers designers a better opportunity to support the high-speed data streams delivered by wireless standards such as 802.11 and DMB.
Few handset designs, however, offer the production volumes needed to support the extremely high costs associated with designing and manufacturing a custom ASIC. Multiprocessor schemes built around proprietary bus architectures limit a designer's component choice to those devices supporting that bus. Given the cost benefits of a modular design where a designer can swap out modules on the same handset to support different 3G cellular or noncellular wireless interfaces to appeal to different market segments, any limitation to design flexibility poses a significant obstacle to a product's success.
The third option is to use multiport memories to support interprocessor communications. Integrating memory and control logic, these devices enable simultaneous access to a common central memory. Each port provides separate control, address and I/O pins that permit independent, asynchronous access for reads and writes to any location in the memory. A 1.8-volt triport device is capable of providing a high-speed, bidirectional interface among three intelligent devices while meeting the handset's tight power constraints. With access times as fast as 55 nanoseconds, these devices support data rates as high as 290 Mbits/s.
From a designer's standpoint, the performance headroom that this interprocessor approach offers is attractive. By using a multiport-based interprocessor communications scheme, they can ensure they have the bandwidth available to support not only current 3G standards, such as cdma2000 1xEV-DO, but also next-generation W-CDMA (HSPDA) running at 10 Mbits/s as well as next-generation wireless data interfaces such as 802.11g running at 54 Mbits/s.
Moreover, that additional bandwidth is crucial for next-generation handsets running emerging multimedia applications like continuous-speech recognition, MPEG-4 imaging and 3-D graphics. Many of these applications will require two to five times the processing power current applications demand, and popular video applications like videoconferencing will require at least 2-Mbit/s data rates between the application and baseband processors.
Multiprocessor communications schemes built around multiport devices offer another crucial advantage: They use a simple, industry-standard SRAM interface. Since the interface is supported by virtually every available embedded processor on the market, this allows designers to more easily build a highly modular system where they can easily swap out components or modules to meet the needs of different wireless standards or market segments. Designers not only enjoy a broader selection of components for their design, but they can more easily reduce their system cost by using the same basic design for multiple markets.
Furthermore, since today's multiport devices support different operating voltages in pin-compatible packages, designers reap multiple benefits from a modular architecture. They extend the battery life of their handset design by swapping out the current multiport devices and baseband processor with lower-power next-generation devices. Or they can migrate their product line to next-generation cellular technology-say, from a cdma2000 1x network to cdma2000 1x EV-DO-in the same way.
Casey Springer (firstname.lastname@example.org) is product manager of the Multi-Port Products Group at IDT Inc. (Santa Clara, Calif.).
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