A multimode wireless design requires careful analysis of process and architecture options to meet the demanding cost, power, size and performance requirements of handhelds. Such devices may include a combination of GSM, GPRS, Edge, W-CDMA, Bluetooth, wireless LAN, GPS and DVB-H.
The key challenge facing designers is the integration of the multimode RF transceiver subsystems into a single chip while achieving the performance requirements of the various wireless standards. Before attempting to design such a single-chip multimode RF transceiver subsystem, a designer needs to first successfully design a multiband GSM/GPRS transceiver, since that is the foundation for the high-volume multimode handset market and has the most challenging performance requirements (better than -102-dBm sensitivity).
The first step is to select the process technology and transceiver architecture that enables the highest level of integration. Next comes the design of the functional blocks that can be shared between the modes; and finally the use of advanced RF/mixed-signal circuits and innovative (often proprietary) digital- signal-processing techniques to address the performance requirements.
CMOS is the process technology of choice for multimode integration, since it leverages Moore's Law and enables the efficient implementation of DSP functions with RF/mixed-signal circuits on a single chip. The viability of CMOS technology has already been demonstrated in a number of commercially available wireless transceivers.
The suitable transceiver architecture for integration in CMOS is either low IF or zero IF (ZIF), which eliminates the need for external IF SAW filters, therefore providing a high level of integration and reducing the bill of materials. Also, since both architectures convert the incoming high-frequency signals directly into low-IF or ZIF baseband signals, they eliminate the need for multiple mixers and oscillators on-chip. They also allow on-chip programmable filter structures to accommodate the variable channel bandwidth to facilitate multimode operation. But designing cellular transceivers based on low-IF or ZIF architecture is not a trivial exercise because of 1/f noise issues associated with CMOS and the dc offset issues associated with ZIF and low IF.
Once the transceiver architecture is selected, the challenge moves to determining ways to share resources on the chip to support the various modes. Some functions are more suitable for a specific architecture.
For example, a low-IF receiver structure is more suitable for GSM/GPRS because of its narrower channel bandwidth compared with W-CDMA, which can be implemented with simpler ZIF designs. On the other hand, dual-mode GSM/GPRS and W-CDMA designs both use frequency bands in the 2-GHz range, making it possible to share frequency synthesizers and filters.
Deciding whether to share the building blocks is also driven by whether the combined wireless standards need to operate concurrently. A concurrent transceiver operation creates significant isolation challenges and often increases the die size of the transceiver design, making it more suitable for implementation with multiple radios.
For performance, the designer must minimize the effect of 1/f noise; design low-noise RF front-end functions; reduce phase noise of integrated oscillators; and provide for high-quality on-chip frequency generation.
These requirements can be met using advanced RF/mixed-signal circuit designs and innovative DSP techniques that perform digital calibration and compensation of the analog nonidealities on-chip.
Robert Fan (email@example.com) is vice president of product management at Berkana Wireless Inc. (Campbell, Calif.).