Wireless basestations and access/aggregation equipment represent infrastructure applications in which power and heat management are critical design parameters. Basestations operate in extreme ambient temperature environments, and digital subscriber line access multiplexers (DSLAMs), mini-DSLAMs, digital loop carriers and related access equipment need to stay cool to remain reliable.
System architects are adopting new approaches to managing power in these kinds of applications. One method is to build physically bigger systems, as conveyed by the Advanced Telecom Computing Architecture (AdvancedTCA) specification, which can dissipate more heat. AdvancedTCA has been embraced as a proof-of-concept platform.
The full extent to which AdvancedTCA will take off for production infrastructure is still unknown. Power, space and cost are major considerations, especially in high-volume access equipment. Some vendors are also wary of discarding years of proprietary know-how and guaranteed upgrade business.
The alternative approach being adopted by designers is to maximize the number of channels per milliwatt. Smart use of new processor features and technology is enabling small-form-factor, low-cost and reliable systems.
Process and transistor technology has been the primary means over the years to higher processor performance, with higher frequencies being the driving force. Recently, however, the focus has moved away from frequency and onto power consumption.
What has driven this change of focus? Until recently, designers' primary power consideration was the ac component, caused by the charging and discharging of gates. The move to 90-nanometer technology and beyond introduces a significant dc power component, often referred to as leakage or static power. Indeed, typical 90-nm leakage current is around two to three times that of 130 nm at the same voltage, and leakage current accounts for more than half the total power of some 90-nm devices.
Lower-power products are being produced in low-power processes, such as silicon-on-insulator technology. SOI reduces parasitic capacitances, resulting in up to 25 percent faster switching frequency or a 20 percent reduction in power. Work is also under way to introduce lower-power, higher-k dielectric material for gate insulators, allowing thicker layers, which are easier to manufacture than the silicon dioxide layers currently used.
Communications infrastructure chip designers also face the same power challenges that higher frequencies bring. Higher-frequency devices require higher voltage supplies and therefore exponentially higher power consumption and dissipation allowances. Increased interrupt latencies, critical in real-time infrastructure, are also a product of higher-frequency processors, which require deeper pipelines to feed the core.
As a result, system designers are moving toward multicore processor architectures, rather than higher-frequency devices, to enable higher system performance while minimizing increases in power consumption. Dual-core microprocessors, originally conceived for computationally intensive applications such as servers, are now being designed and deployed in embedded applications.
In addition to the increased channels per milliwatt, these dual-core devices reduce system bandwidth, latency and system bottlenecks through higher integration. On-chip memory controllers, for example, are improving processor-to-memory latency by three to four times.
Better memory control
Memory is also an area for power savings. Smarter memory controllers can negate the clock-enable signal when no transactions are pending to the memory and when no memory refreshes are scheduled. This typically reduces memory power consumption by up to 20 percent.
Another system design technique to reduce the power burned by a memory device and its termination resistors is to leverage the remote booting and control of processors when connected together in a clustered arrangement. High-speed interconnect/fabricschemes, such as RapidIO, enable processor nodes to be completely controlled via their connection to the fabric. This eliminates the need for flash memory for booting and assorted complex programmable-logic devices to drive reset and interrupts.
Even legacy mechanisms like Ethernet controllers now have the basic capability to initiate an FTP-based boot without additional flash memory. The elimination of flash on every line card saves around 3 watts for a 32-line DSLAM.
Many processor power-saving oppor-tunities have resulted from intensive focus on extended battery life in mobile computing. Dynamic frequency switching allows software to change a processor's core frequency on the fly within a single clock cycle. There is no need to insert idle cycles or reset the device, and the processor remains fully functional. The typical power savings is 45 percent.
Embedded apps have driven another set of heat-reducing features. Some processors integrate dynamic power management, which automatically withholds power to execution units when they are not being used. Instruction-cache throttling is another example; by reducing the maximum instruction execution rate, this technique maximizes the impact of dynamic power management.
Low-power modes are often overlooked and underexploited. With today's high-performance embedded processors, it is no longer just a question of "on" or "off"; new processors offer multiple states, each with associated settings for processor clocks, phase-locked loops and responses to snoops or interrupts. For example, it is common in sleep mode for the PLL to be on while internal clocks are off. Optimized software design that takes full advantage of available features will enable additional power savings.
Single-instruction, multiple-data engines also offer returns on software investment. SIMD engines enable highly parallel operations, allowing for simultaneous execution of multiple operations in a single clock cycle by means of instruction-level execution units that operate concurrently with existing integer and floating-point units.
Results certified by EEMBC show speed enhancements of 12x over scalar processing for the telecom benchmarks. Those include algorithms such as Viterbi decode and convolutional encoding, which are used in wireless basestation baseband processing. The gains are achieved with an increase in processor power of only 5 to 10 percent. The results are gained by coding in C, minimizing the need for hand-code assembly.
High-volume, power-sensitive access applications, such as DSLAMs and wireless basestations, will almost certainly remain outside the Advanced TCA framework. For many communications system designers, the focus is to achieve low power at an optimal performance level.
Designers of AdvancedTCA-suitable applications, such as wireless radio network controllers, are also benefiting from embedded low-power processors and software techniques to maximize their communications channels per mW.
Richard Low (firstname.lastname@example.org) is a PowerPC system architect at Freescale Semiconductor Inc. (Austin, Texas).
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