Gigabit line cards are being tasked with accommodating a plethora of physical-layer transceivers, ranging from octal-type Fast Ethernet versions to copper- and fiber-based Gigabit Ethernet transceivers. At the same time, designers are looking for boards to handle media access control and higher-layer functionality.
To meet line card demands, designers are turning to detachable modules, such as Xenpak, X2 and Xpak, that combine PHY and MAC functions in the same package while meeting a tight power budget approaching 1.5 W. This move places severe restrictions on the power consumption of PHY transceivers and, in turn, forces silicon vendors to develop new techniques for reducing power in PHY components.
To solve the problem, silicon vendors are turning to "cool IC" designs and methods. Cool IC design is a bag of tricks that includes sophisticated signal-processing techniques, low clock architectures, optimal analog and digital partitioning, self-adjustable power-saving modes and advanced fabrication process technologies.
In cool IC design, power optimization is considered in every phase of transceiver design: architecture and algorithm selection, analog/digital partitioning, circuit design and layout, and semiconductor fabrication process selection.
During architecture and algorithm selection, improving the receiver sensitivity reduces transmit amplitude levels and thus provides one way to reduce power. Standards guidelines typically mandate the minimal transmit amplitude that should be adhered to.
Equalization is another common function used in transceivers that deal with frequency-sensitive channels. In system design, several basic trade-offs occur, including how many taps will be used in the decision feedback equalizer (DFE) and feed forward equalizer (FFE) sections. Implementing the equalizer in the digital domain results in DFE taps with lower power consumption since they are implemented with adders rather than costly multipliers.
Typically, equalizers are implemented as adaptive filters based on the least mean squared (LMS) adaptation algorithm. Instead, one can use signed error LMS, or the logarithm of the error. The convergence times and steady-state mean-square error of the latter approaches are similar to regular LMS but are simpler to implement and consume less power.
Another approach is to decimate in time the adaptation and updating coefficients every "nth" clock rather than every cycle. Update every clock at startup to gain fast convergence, and relax the update rate after initial convergence through the use of a gated clock design.
First-generation PHYs are challenged in meeting performance requirements using even the most advanced process technology. It is tempting to implement more functionality using an analog rather than a digital FFE.
However, the life span of PHY transceivers over multiple generations should be considered. During this period there may be several fabrication process technology advances. Therefore it's beneficial to put more functionality in the digital domain, allowing greater power consumption reduction with the scaling of fabrication process geometries.
In addition to partitioning, advanced CAD tools can be tapped to improve power performance. These tools typically include power compilers that can assist in estimating various architectures' and algorithms' power consumption.
After layout and verification of timing constraints, designers can use CAD tools to estimate the capacitive load of each gate and revert to low-power cells, checking that timing constraints are not infringed. This process is automatic in advanced CAD layout tools.
Power grid design is also important. An aggressive power distribution grid implies that blocks are spaced farther apart, increasing capacitance and, consequently, power consumption.
The shrinking of fabrication process dimensions results in lower power consumption through several mechanisms. The most obvious is the lowering of supply voltages used for the digital part; power consumption is linearly related to the square of the supply voltage. For instance, migrating from 0.15 to 0.13 micron reduces the supply voltage from 1.5 to 1.2 V, yielding a 36 percent power reduction.
The second mechanism is based on observations that the power consumption of each gate is linearly related to its load capacitance. Since physical dimensions are smaller for advanced processes, the capacitance that each gate drives becomes smaller, resulting in reduced power consumption.
A third mechanism involves improved process speed for smaller geometries, allowing for more relaxed timing constraints. This is exploited with low-power cells or streamlining data path pipelines. Advancing from 0.15 to 0.13 micron yields a 60 percent reduction in power consumption.
While state-of-the-art internal architecture design is mandatory to achieve low power, the IC vendor's contribution goes much further. Integrating external components, designing a multimode chip that supports a variety of protocols and operation speeds, operating with the lowest possible power supply voltage, and advanced packaging that ensures good power dissipation are only a partial list.
The concept of SoC design is certainly not new. Neither are the concepts of low power and high performance new in SoC designs. What is new, and challenging, is achieving combined requirements.
Racing to the best feature solution might miss the power target. On the other hand, implementing the lowest possible power consumption delivers a lack of functionality.
In new markets, performance is paramount, and power and integrated functionality are secondary. Upon widespread adoption, power consumption dominates. As markets mature, the performance and power duet must be accompanied by support for multiple protocols, integration of peripheral components and greater programmability.
For example, initial transceiver offerings for the 10-Gbit/s-over-copper CX4 standard doubled the operation range (from 15 to 30 meters). Second-generation devices focused on further power reduction and an expanded set of features, such as an on-board clock oscillator and multisource agreement (MSA) registers, along with the elimination of several external components.
The net effect is significant system power and cost reduction. Overall power reduction at both the chip and board levels enabled migration from Xenpak to X2/Xpak form factors, important for higher port densities on line cards.
Cool IC design practices substantially reduce power consumption, even in highly complex communications devices. An increasing level of on-chip system integration enables further, dramatic power savings. Cool ICs rely on many "tricks" spanning architectures, design, packaging and advanced fabrication process technologies. The outcome is to open up even greater SoC integration possibilities in the future.
Dimitry Taich (firstname.lastname@example.org) is an applications manager at Mysticom Semiconductor (Mountain View, Calif.)