by John Weekley, Director of Business Development, Synopsys, Inc., Mountain View, California
The design productivity gap has been widely discussed for a decade. Intel processors and other leading edge designs, like graphic processors from NVidia and ATI, achieve optimal use of available technology. But, the typical ASSP and ASIC designs are not taking advantage of CMOS technology, and are not achieving optimum unit cost per function. As a result of this problem of lagging design productivity, the ITRS identified the need to create roadmaps to improve the industry’s design productivity.
The ITRS forecast for increased use of semiconductor intellectual property (SIP) accounts for 75% of the design productivity improvement in the 2003 Roadmap. In particular, the addition to the productivity roadmap of Very Large Block Reuse is forecast to keep design cost under control, by boosting productivity to 600K gates per engineer per year.
|Year ||DT Productivity Impact ||Gates Per Designer per Year ||Description |
|1990 || Design Technology ||4,000 || |
|1993 ||In House Place and Route || 5,550 || Automated Block Placement and Routing |
|1995 || Tall Thin Engineer ||9,090 || Engineer can purse all tasks to complete a design block from RTL to GDSII |
|1997 ||Small (2K-75K) Block Reuse ||40,000 ||Blocks from 2,500 –74,999 gates |
|1999 ||Large (75K-1M) Block Reuse ||56,000 ||Blocks from 75,000-1M gates |
|2001 || IC Implementation Suite || 91,000 || Tightly integrated toolset that goes from RTL synthesis to GDSIII through IC palace and route |
|2003 || Intelligent Test Bench || 125,000 || RTL verification tool (cockpit) that takes and ES-level description and partitions it into verifiable blocks, then executes verification tools on the blocks, while tracking and reporting code coverage |
|2005 || ES Level Methodology || 200,000 || Level above RTL, including both HW and SW design. It consists of a behavioral (where the system function has not been partitioned) and an architectural level (where HW and SW are identified and handed off to design teams). |
|2007 || Very Large (>1M) Block Reuse || 600,000 ||Blocks >1M gates; intellectual-property cores |
Based on the 2003 ITRS forecast, combined with industry projections for design starts and design sizes by process, we can project that about 100 billion gates of reused logic blocks will be integrated into new IC designs in 2007. Put another way, more than 100,000 blocks of re-used logic, each with an average of 100,000 gates will be needed to meet the design productivity goals of the ITRS in 2007. Where are all these gates going to come from? IC designers will have to procure more re-usable IP, and they will have to embrace a methodology that uses blocks of IP that are an order of magnitude larger than they use today.
It has become a widely accepted business practice to outsource or subcontract for products and services used in inbound logistics that are not identified as elements of a core competitive competence. The rapid growth of the Fabless Semiconductor business model is an obvious example of this trend. In this Fabless model, companies integrate the disaggregated components of their own value chain with the unique competitive elements of their own creation to deliver a differentiated solution to customers. The features, quality and cost of these acquired components of the Fabless product are literally integrated into the competitive attributes of the final semiconductor.
Philippe Magarshack of ST authored this view of the IP Pyramid in December 2003
Foundation IP and Processor (“star”) IP are adopted and used pervasively within each IC design company’s design flow are the base of the IP pyramid. This foundation level of commercial IP is dominated by ARM and Artisan. Clearly, most of the traditional IDMs also have their own proprietary foundation IP, but may also license similar foundation IP for specific purposes. The standards-based IP segment includes widely licensed commercial IP like USB and PCI. It is very rarely either strategically or economically justified to make this IP in-house. Synopsys is the clear market leader in this segment. The top of the IP Pyramid is application specific IP, which may be strategic and proprietary. Application specific IP is generally developed in-house because it is not available as commercial IP.
The SIP Make vs. Buy decision is a “strategic” decision, because it has significant consequences that have long-term impacts on the productivity, resources, risks, structure and profitability of the buying company. If your strategic analysis concludes that it will be feasible to procure IP, it is ALWAYS going to financially better to buy than to make. Nevertheless, a model and methodology is provided to allow you to prove this to your management, if required. The cost of ownership model will also be useful in comparing the total cost of ownership between potential vendors of IP.
There have been many published studies on the cost justification models for software reuse. It is beyond the scope of this overview to discuss them, but for further detail you may consider the 16 cost models that are reviewed in Managing Software Reuse by Wayne Lim. The obvious costs to buy IP are the vendor’s license fees and royalties. The larger (but more difficult to estimate) ‘hidden’costs also need to be considered in the model. In order to keep the cost model presented here simple, only the expected internal cost to design, support and maintain the IP are calculated, along with potential lost profit resulting from a significant design error.
An Excel spreadsheet is a flexible tool for forecasting future “financial” costs of the alternatives. The key economic input assumptions variables that are used in the ‘make versus buy’ evaluation and total cost of ownership calculations are briefly explained below.
|Fixed Engineering Costs Per Year || 2004 Typical Value |
|Average loaded salary and benefits cost per engineer per year ||$228,200 |
| Additional opportunity cost hurdle ; % per year to justify engineering ||50% to 200% |
|EDA and workstation tool cost per engineer per year (loaded) ||$164,850 |
The cost figures shown here are taken from the assumptions listed in the ITRS roadmap. Many people express an immediate reaction “We don’t pay our SoC design engineers $228K!” But, on top of the obvious salary paid, you must add adjustments to include the hidden total compensation composed mostly of health benefits, government payroll taxes, retirement contributions, employee stock options, stock purchase plans, travel, business expenses, management overhead, support overhead, and facilities. You may choose to use a different value, just do your due diligence. Similarly, the $164K per year per engineer for EDA and workstations is composed of the outright tool licenses, plus the computing hardware, network and IT support, and internal CAD tool integration expenses.
The model also includes a factor for engineering “opportunity cost”, which is used to declare a value adder on engineering investment. This percentage factor is a mark-up on in-sourced engineering as consideration for the expected ROI, ROA, IRR, Revenue per employee, and other productivity metrics that demand consideration for the opportunity to use R&D engineering for other tasks. The 50% adder shown here would be the low end of the contribution margin expected in a pure work-for-hire engagement. A more typical benchmark used in developing commercial products, is an expectation of a return (profit divided by investment) of 5X to 10X, over the life of the product.
|Engineering Productivity Assumptions ||2004 Typical Value |
| New Gates per Engineer per Year ||91,000 |
|Design For Re-Use Impact on Productivity (divide by) ||3 to 5 |
|Annual Support and Maintenance engineering as % of original effort ||15% to 30% |
|Probability that an error in the Core “Make” option will require a Re-spin ||10% |
Productivity is projected by the ITRS to increase from 40K gates per engineer year in 1997 to 600K gates per engineer year in 2007. Adoption of increasingly larger scale blocks of re-useable IP accounts for 75% of this productivity improvement. If your loaded salary cost estimated in the previous section is significantly lower than the ITRS benchmark, ensure that you carefully justify the productivity and quality assumptions in this section! Critics of the recent trend to ‘offshore’ IC design engineering jobs in order to reduce salary and benefit costs argue that the impact of actual productivity and quality of the work-product of these cheaper locations is unproven.
This productivity estimate is a critical measure of the average output of the engineering team, based on their background and experience in similar tasks. Engineering productivity varies widely; some research shows that the top engineers produce 20 times as much work product as typical engineers. The accuracy of estimating the total amount of effort to complete a project, rationalized against the specific manpower that can be assigned to a project varies directly with the experience of the people doing the estimate. Estimates often vary by orders of magnitude!
Designing re-usable IP requires significantly more effort that designing IP for a single use. Re-usable IP is engineered to conform to the coding styles in the RMM or QIP, with extensive configurability, verification, portability and documentation to improve the future user’s ability to adopt the IP. Most experts believe that it takes three to five times more effort to create truly re-usable IP.
One significant cost for enabling reusable IP is on-going support and maintenance. The IP will continue to evolve over use, based on bugs that are found and corrected, and updates and enhancements that are a given in any evolving technology. The IP will be stale, obsolete, and unusable unless resources are dedicated to maintain it. Likewise, when a new design team begins to use a re-usable IP block, their productivity requires a support resource to answer domain specific questions, and they will want some expert know-how from a support team to assist in configuration and integration.
If you “make” the IP yourself, you need to estimate the probability of additional costs and lost profits due to an error in the design. No IP can ever be proven to be bug-free, but the likelihood of a significant defect declines as a function of the quality of the verification effort, and the number of actual silicon implementations. Robust verification testing using techniques like constrained random verification (CRV) can also reduce the probability of defects in a core. As a figure of merit, it has been reported in a widely quoted research study by Collett that about 70% of all new IC designs have a functional error that require a silicon re-spin. You need to make a realistic estimate on the probability that the IP core that you “make”, in its first use as instantiated, will have a significant error. The potential impact on costs and profits of this estimate is one of the most important considerations in hidden cost. A typical software program has an initial bug rate of one defect per twenty lines of functional code, Microsoft reports one bug per thousand lines, and the Space Shuttle reportedly flew with a software defect rate of one bug per 400K lines of code. HP Software Technology division reported 4.1 defects per thousand lines of new source code, versus 0.9 defects per thousand lines in reused code.
This diagram illustrates the conceptual trade-off between productivity and quality. Pushing for high productivity generally results in lower quality, and vice versa. It also illustrates that the productivity and quality of the work-product improves with additional reuse. The probability of a major bug increases exponentially with the complexity of the IP, and declines exponentially with IP maturity, after significant effort investing in the execution of a robust test plan, and actual silicon proof in a real system.
|IP Core Re-Use Assumptions || 2004 Value |
| Number of designs my company will do with this core per year || |
|Number of years my company will use this core || |
|Average total unit volume per design per year || |
The model requires some inputs for the expected usage of the IP.
|Core License Cost Assumptions ||2004 Value |
|Core IP Complexity (Estimated Number of Gate Equivalents (2NAND)) || |
|Initial License Fee || |
|Per Design Use Fee || |
|Production Royalty per Unit || |
|Test Environment License Fee Per Year || |
|Supplier Support and Maintenance cost per year || |
|Core Training and Consulting Cost per year || |
|Probability that an error in this Core that I “buy” will require a Re-spin || |
Additional inputs to describe the expected license costs for acquired IP are needed.
|IC End Product Assumptions || 2004 Typical Value |
|Cost of Mask Set and Proto Wafers ||$800,000 for 130nm |
| Impact to revenue of initial products caused by an error in Core ||50% |
| Average market value/ selling price of initial product ||$20 |
| Expected Gross Margin of My initial product that includes the Core ||50% |
Finally, some estimates of the NRE costs, and end IC product business outlook are input.
Three different scenarios were evaluated with spreadsheet models in detail to provide examples of how to evaluate IP using the Make versus Buy model, including:
- A USB 2 Host in a High Volume PC Chipset (ASSP)
- Infrastructure IP that will be broadly used in many designs- AMBA AHB bus and peripherals
- A relatively low volume customer specific design (ASIC) example (worst case scenario for IP)
The result from each of these scenarios demonstrated that it was clearly economically better to Buy the IP, than to Make it. But, since total revenue of the market for commercial IP is less than one percent of the semiconductor market, it is obvious that most companies today continue to make most of their re-usable IP.
Is this because the prevalent attitudes about IP include NIH- (not invented here thinking), paranoia, or post-traumatic stress from previous experiences with bad IP? Or, is it because the process of acquiring IP is so painful, time consuming, and visibly expensive? As an industry, we need to identify and address these impediments, to embrace the productivity improvements that the ITRS has forecasted, based on IP re-use. Each IC developer should adopt a process for evaluating IP, and IP suppliers. This evaluation must be cross-functional, and should include the IP users, technical experts, and business decision makers.
One aspect of the technical evaluation of IP is the subjective estimation of “Quality”. Quality literally means initial conformance to a specification, but in measuring Implementation IP and Verification IP, judgments about workmanship, design flows and procedures, verification testing, documentation, configurability, testability, reliability etc. may be included in “Quality”. The recent VSIA QIP criteria are built on the guidelines based on the Reuse Methodology Manual (RMM) written by Pierre Bricaud and Mike Keating of Synopsys, with new contributions from Agere and ST. The original RMM-based OpenMore worksheets, and the more recent VSIA/FSA QIP worksheets, attempt to put a numerical score on re-usability, and quality. The QIP worksheets provide a starting point for evaluating IP, but the questions are almost entirely focused on technical and user level issues. The current form QIP will not be useful for business-oriented “economic” decision makers in a cross-functional team, because it does not address these issues in a meaningful way.
The business issues that are not included in the QIP also require a thorough due diligence. The critical question for people responsible for a profit and loss statement and cash flow is: “What is the return on investment (ROI)?” Sales and Marketing should provide a forecast for the revenue part of that Return on Investment equation, and the economic decision maker should ensure that a qualified professional evaluates the “investment” end of the equation. This due diligence analysis is largely a subjective evaluation of the vendor, along with some projections of many potential “hidden costs” that will impact calculations of Total Cost of Ownership. The following checklist is offered for your consideration:Go No-go Red Flag Questions
Other Questions That Will Impact Total Cost of Ownership
- Legal Issue Red Flags
- Does the supplier have clear title to the IP?
- If the supplier acquired the IP, can they satisfy us that it is clear of all legal challenges?
- If the supplier is brokering this IP, can they satisfy us that it is clear of all legal challenges, and will they accept responsibility for protecting me?
- Are there any potential patent, copyright or trade secret issues with my use of the IP?
- Can the supplier be held legally and financially accountable for this transaction?
- Can we negotiate a reasonable commercial license quickly?
- Supplier Due Diligence Red Flags
- Does the supplier have the history, reputation, and financial capability to fulfill future obligations?
- Am I satisfied with the supplier’s ability to support his business model, as evidenced by a D&B report, or review of Financial Statements? Some key indicators of financial health are Quick Ratio, Current Ratio, Cash Flow, and Debt to Equity Ratio.
- Do I trust the integrity of this supplier, and the individuals that I am dealing with (you can’t make a good deal with bad people)?
- How much support and maintenance burden will the supplier actually provide?
- Does the supplier have adequate IP domain-specific experts that will be focused on support and maintenance of the IP?
- What is the supplier’s human infrastructure and software for support and maintenance?
- If the vendor is a broker, who will respond to support issues?
- What is the supplier’s historical commitment to providing on-going maintenance?
- What is the supplier’s historical performance in providing support for IP?
- How much risk would I be taking that the IP may have a significant defect?
- How many production IC designs is this core in?
- How many production IC designs similar to my application is this core in?
- How extensive is the proven compatibility and interoperability of this core with other IP on my chip, and in other systems that interoperate with my chip.
- What does the current and historical bug tracking indicate about the quality and maturity of the IP, (or the quality of the bug tracking)?
- If I encounter a serious problem with my chip design that involves this core, can I count on this supplier to be responsive?
- What is my perception of the probability that this core will have a defect that will impact production of my design?
- What is my perception of the probability that this core could have a defect that will cause me to recall the end product, or similar disasters?
As this example shows, those obvious fees are just the tip of the proverbial iceberg. The potential impact of design re-spin costs, lost opportunity costs and other hidden costs need to be quantified based on your best judgment. The business model allows you to quantify these costs.
‘Buying” IP is similar to getting a new car. Based on your anticipated future needs, you may want to evaluate renting, leasing, or buying, with many options in financing. Similarly, once you have made the decision to buy IP, you should negotiate a deal that fits your financial needs. In IP business models, the relevant license terms often include:
- Single Use License- right to use the IP for a specific design
- Re-Use License- right to use the IP for a subsequent design
- Multiple Use License- right to use the IP for a number of future designs
- Royalty on Production- payment of an amount based on production, typically a percentage of unit price of the IC, or a fixed amount per IC.
- Buyout- pre-paid right to use the IP and sell production ICs without limit, typically for a fixed period of time, like 3 years.
- Subscription License- right to use specific IP , and sometimes a library of IP, and to sell production ICs without limit during a term, with fixed regular (annual or quarterly) payments
- Support and Maintenance Fees- support fees cover user questions, and bug fixes. Maintenance provides access to updates and enhancements during the term.
The economic impact of the selected IP supplier’s business models can be compared. Here is an example of a total cost of ownership model used to project a vendor’s license model, support, maintenance, and risk profile. Most suppliers offer flexibility in the final negotiation of a business model payment arrangement.Conclusion
Increased use of IP blocks are a key forecast of the ITRS that results in 75% of the productivity increases by 2007. Buying core IP is a critical “strategic” decision, that requires cross-functional due diligence in the evaluation and selection of vendors. Economic models should be used to estimate the potential total cost of ownership for make vs. buy decisions. If quality IP is available from a trusted vendor, the cost model always justifies “buying” quality commercial IP over ‘re-inventing the wheel’. A set of additional areas of interest for business and financial analysis has been offered, and a spreadsheet model for evaluating potential total costs. Ensure that your team does a full due diligence on the hidden costs and red-flag risks for potential vendors. Don’t be a spendthrift, and make an informed decision.