| Analog and mixed-signal design are often regarded as representing significant bottlenecks in system-on-chip (SoC) design. A manually intensive process that has proven difficult to automate, the belief is that analog design productivity improvements are extremely difficult to obtain. |
In addition, compared with digital design, analog design productivity is difficult to measure. You can measure digital productivity in terms of the number of transistors, but for analog design this is a highly misleading metric. Complex mixed-signal blocks may need tens of thousands of transistors, not the millions of transistors in digital blocks.
However, the area consumed by such blocks can account for more than 20 per cent of the overall IC area. The skill lies not in generating transistors but understanding the relationship between those active devices and the on-chip passive components, such as resistors and capacitors, and the metal tracks that join them.
Digital designers are able to make use of highly automated synthesis and layout tools. The use of standard-cell design techniques has underpinned the drive to high levels of automation, as tool vendors are able to use the standard cells to provide a common base for their tools across many different processes.
In analog design there are no truly standard cells. There are standard functions, such as bias generators and operational amplifiers. But there are many different architectures and topologies for these functions and each has to be tuned to a specific process.
Automation can still work for analog design
This does not mean you cannot make automation work for you. Synthesis is a two-stage process for analog design. The first part, and the hardest to automate, is the topology selection and circuit optimization process. The second is generating the individual circuit components and laying them out in the physical design.
The first part is where most of the engineer skill lies. It is difficult to produce a synthesis tool that will make such high level decisions as well as an experienced analog designer.
The second is where much of the tedium in manual layout lies, and where simple and easily avoidable mistakes can be made. It is this second part of design synthesis where custom automation techniques can make a big difference to productivity.
A number of analog layout editors, at both ends of the cost spectrum, have programming interfaces that let the designer implement libraries of functions that automate the job of generating structures and circuits. Some use obscure proprietary scripting languages, but there are a number that use the popular C language, making them accessible to many engineers and helping to avoid learning curves when new engineers start to work on a design.
These tools also allow the engineer to build user interfaces that allow macro parameters to be entered and fine-tuned. The user interface and the underlying code can be as complex as the designer wants to make it.
When it comes to writing analog-cell generator macros, the highest efficiency is in components and cells that will be used a great deal across a number of projects so that the design time invested will be recouped.
But that's not the only consideration. Where a design is likely to be subject to process changes over time, a parameterized cell can dramatically reduce the rework needed to adapt the design to the new process. Even when the design process is not likely to change, the design often requires many small variants on a standard part.
Again, parameterized components and cells can be adapted fairly easily to implement these variants without have to create and run new scripts for each. It is also worth bearing in mind that, particularly for new processes, foundries often change design rules almost weekly, requiring changes to layout specifications with respect to line widths and spacing etc. Macros can be modified quickly and easily to accommodate these rule changes.
Figure 1 — Macros can be quickly modified to suit process changes or to create part variants.
At first sight, it may seem that writing macros to create parameterized components and cells is only worthwhile for more complex components. However, process limitations mean that even resistors, inductors and capacitors are subject to a fair number of design rules to ensure that they can be created to the required degree of accuracy within the foundry's process limitations.
Also, in many analog circuits, such as amplifiers, good matching between devices is as important as achieving precise absolute values if unwanted offset voltages are to be avoided, and good shielding is needed to protect critical nodes from disturbance. These considerations apply to both active and passive components when developing the layout.
Even simple components are time-consuming to create manually
For small resistors, straight segments can be used; some processes also support 'dog-bone' shapes. The final resistance value of a straight segment resistor is dependent upon the length, width, thickness, sheet resistance and sheet resistivity of the segment.
Folded serpentine structures are normally deployed for larger resistance values to achieve better matching and to minimize silicon die area. Here, corners can cause matching problems because they are more sensitive to process variations and it is a good practice to use metal, rather than polysilicon, to make the turns in order to achieve optimum matching.
The serpentine resistor is therefore constructed from a series of rectangular segments and, for accurate matching between resistors, the same geometry must be seen from the top and bottom. Both wet and dry etching processes cause an undercut effect that is less prominent when dummy resistors are created on each side of the main resistor segments.
Interdigitization, as shown in Figure 2, is a common way of mitigating process variations to achieve better matching. Clearly, the layout of resistors can involve many parameters, and the better analog tools facilitate the creation of a resistor generator where parameters can be entered each time the macro is run to quickly generate the required resistor.
Figure 2 — Structures such as interdigitized serpentine resistors with dummy strips are complex enough to warrant investing time in writing generator macros.
Capacitors in ICs are of a parallel plate type. Most are of metal-insulator-metal (MIM) construction. Where accuracy is important, dummy elements around the outside of the 'real' capacitor elements are again often used to improve process accuracy by mitigating the undercut effect. Some newer processes allow a dummy strip around the capacitors instead of dummy capacitors; this can reduce the silicon area needed to avoid process variability problems.
The practical size of MIM capacitors is limited by the weight of metal that can be sustained by lower layers, as the weight of the metal can compress the oxide layer more in the middle than around the edges. This, and process variables such as oxide thickness, mean that capacitors often need to be broken into smaller elements, usually laid out in a common centroid structure.
There is a trade-off here because larger single capacitors exhibit less fringing effect at the edges of the metal, while the increased total length of edges in a capacitor matrix increases this problem and means that more silicon area has to be used. However, with appropriate interconnect, the multi-element approach has the added benefit of eliminating mismatches between two or more capacitors because the layout can be arranged such that process variables affect each capacitor equally. These components take a long time to draw by hand, but it is a simple matter to write a macro that generates a matrix of such capacitor elements.
Figure 3 — It is a simple matter to write a macro that generates a matrix of capacitor elements such as those in this common centroid construction.
Building an inductor generator is a similar matter. In this case, the generator macro will use the number of turns in a spiral, track width and spacing to create the inductor. The macro can add connections in other layers to ensure that the inductor can be connected easily to the rest of the circuit.
Inductors are normally created in the top-level metal where most processes allow the highest thickness of metal. The use of thicker metal minimizes resistance and maximizes the inductor's Q-factor.
Parasitics and stray capacitance, both laterally and vertically, reduce inductor Q-factors. The problem can be mitigated to some degree by using just outer spirals, which create most of the inductance, and avoiding the use of inner spirals that contribute little to inductance but more significantly to parasitics. For higher inductance values, inductors can be created on top of each other and connected in parallel if care is taken in layout to minimize cross coupling and capacitance.
It can also be useful to create patterned shields beneath inductors. Cross coupling then creates a current flow in the shield that is of the opposite polarity to that in the inductor, thereby minimizing the inductor-to-substrate capacitance and maintaining Q-factor.
Once again, an apparently simple component can benefit greatly from macro generation; in creating high-Q inductors in an IC design there can be a lot more parameters to deal with than first impressions might suggest.
More complex components are where the power of a language such as C, coupled with a rich programming interface to the underlying analog tool, delivers the greatest benefits. Basic transistors are easy to draw, and indeed copy from one design to another. However, carefully matched circuits that have high process tolerance will be much more complex elements.
It is often better to use wide, multi-fingered transistors where accuracy is vital. In a matched design, the fingers of the two transistors will be interdigitated. This structure is simple to understand but tedious and error-prone to draw.
In practice, most of the issues discussed with respect to laying out passive components are applicable, with greater complexity, to transistors; common centroid structures, the use of dummy devices on the ends, matched interconnect and the possible use of guard rings all need to be taken into account. A macro can save much time here, while guaranteeing that the connections to each well and gate are to the right supply and signal lines, that they are the proper width, and that the device has the appropriate well and gate spacing characteristics.
Once basic libraries of transistor generators are in place, particularly those that create matched elements, it is possible to extend the use of macros to build local voltage sources using current mirrors and similar structures automatically. Some have taken this much further, having implemented complete, commonly used circuits such as bias generators. This approach nears cell synthesis in terms of programming complexity, although the most difficult choice — that of topology — is left up to the designer.
In general, process changes can be accommodated very easily within the parameterized cells, the possible exception being bipolar transistors. These are notoriously process-dependent, so more work is needed to modify cells.
Design them, buy them or get them free
Parameterized cells for standard building blocks are available free of charge for the design flows of many EDA vendors. Either the vendors themselves provide them, or the foundry may. Other vendors will normally have some standard components for sale and will offer a development service for others. Alternatively, designers can choose to create their own.
For an experienced C programmer, a simple resistor or capacitor can probably be created in a couple of hours, with more complex transistors taking perhaps up to a couple of days. Frequency of use, the number of component or cell variants needed, the controllability of foundry processes and the likely frequency of process or design rule changes will be the key determining factors as to whether the up-front effort will produce a worthwhile return in terms of time savings down the line, or fewer design errors.
Although analog designers do not have the large number of tools at their disposal that digital logic engineers have, it does not mean that large parts of the process cannot be automated. Even apparently simple passive components require numerous parameters to be defined to accommodate component variants, process variability and potential design rule changes, so layout automation is even of benefit here.
The development of parameterized components and cells takes more upfront investment from the analog design team, or can add some cost where these are developed by the EDA vendor, but the results are well worthwhile and ensure that the designers can use their hard-earned knowledge and experience to best effect, instead of spending valuable time simply pushing polygons.
Nicolas Williams, Product Manager at Tanner EDA, works closely with customers and development to produce EDA solutions for today's design problems. He also contributes to product development, IC design, design kit development, and product direction. His field of specialty is analog EDA and analog, mixed-signal, and RF IC design.