SoC package design takes 'bottom-up' tack

As system-on-chip designs migrate to nanometer silicon, packaging technology is challenged to keep pace with the integration and performance capabilities offered. Nowhere is this more so than in communication and networking products, which are continually driving the performance requirements of semiconductor designs.

Meeting system design challenges of improved performance, lower cost and better time-to-market takes "bottom-up" co-design. IC design and its support infrastructure can no longer develop independently of the system environment. Products and their performance must be characterized together to ensure the most robust design solution.

Traditional ASIC designs in 0.35- and 0.25-micron process technologies were typically achieved in relatively independent steps. System design architectures were defined by the gates and memory capabilities of ASIC designs. Later, enhanced cell-based architec-tures incorporating multiple intellectual-property (IP) elements, resulting in

complex SoC designs, provided multiple system-level integration options. Most standard package solutions available at the time were sufficient to support the performance of the silicon device.

Over the past decade, however, silicon technology has continued to follow Moore's Law, and sometimes surpass it. Packaging has struggled to keep up with silicon's integration and performance. Worse, pc-board technology has lagged behind both silicon and packaging technology.

High-speed signaling today requires an understanding of the transmission-line environment from the silicon transistor level to the system backplane. Integrated tools and methodologies from pc board to chip design provide an automated approach, ensuring correct design by construction.

In many cases, IC floor planning and layout are dictated by the pc-board routing constraints seen in the package layout. Since this is an increasing design trend, the next logical step is to develop a design system that incorporates the system-level constraints and ties them into the chip package design process.

Today, few tools can model and design the system accurately and efficiently. Although this challenge is present for many product types, communication products such as networking/Internet switches and routers continuously raise the bar. The need to provide traffic management to terabits of data transfer requires seamless design from the input of the box to the output.

HSTL buffer for high-speed quad-data-rate memory interfaces.

Communication and networking products use several I/O types and protocols. Each has unique transmission-line requirements, whether they are single-ended I/Os for memory interfaces or differential signals for LVDS and serdes.

High-data-rate applications continue to drive system bandwidth higher, creating the need for high-performance interconnect for line cards, chip-to-chip paths and switch fabrics. Taking parallel standards into the serial domain lets manufacturers create systems with lower signal counts, simpler cabling and higher performance.

But this higher-speed performance affects signal integrity not only in the ASIC but also in the package and the printed-circuit board.

Without careful design practices, program delays and rework will be inevitable. The impact on time-to-market could lead to lost revenue.

Electrical modeling and simulation are key components of system co-design, as the first step in determining component and system performance and its impact on IC and pc-board design. Optimizing package design to provide the best electrical environment for high-speed signals is done in concert with the circuit designer and IC designer.

Modeling and simulation
Assuming models and simulations correlate with measured data, simulations enable an efficient, cost-effective feedback mechanism, driving circuit design, final die floor plan and package design.

Parasitic extraction is typically done with 2-D/3-D quasistatic electromagnetic field solvers, simultaneously extracting signal traces and supply (Vss/Vdd) planes.

In the case of I/O and package, the two models need to be incorporated together and simulations performed. Depending on the speed of the I/O type, appropriate modeling techniques must be incorporated. These include 3-D lumped/distributed HSpice-compatible models for system-level simulations and 2-D/3-D cascaded models using EM-field solvers for high-bandwidth signaling.

Simulation results can modify the circuit design or package design to achieve the desired result. For example, the signal from a high-speed transistor logic (HSTL) buffer typically used for high-speed quad-data-rate memory interfaces exhibits a very poor eye diagram. The collapse of the eye is a result of excessive crosstalk, ground bounce and reflections on the Rx and Tx signals.

Although the signals are clocked at 100 MHz, fast buffer edge rates combined with poor transmission-line design in the pc board cause the timing margin of the entire memory interface to fail. To mitigate this problem, the entire transmission line from the IC to the receiving memory device must be modeled and simulated.

Design modifications may include I/O buffer, such as slew rate control; I/O layout on the die and optimization of the package to minimize crosstalk between signal traces; and controlled-impedance lines and impedance matching on the pc board (far-end termination).

Modeling and simulation techniques when developing I/Os, coreware and packages is essential to ensure each piece of IP works together in an SoC.

Package optimization
When designing an ASIC or SoC, a key component of the co-design process is the package. Even new IP elements such as serializer/deserializer cores must be designed with the package in mind to ensure a seamless link from die through the package and out to the pc board.

Stan J. Mihelcic (smihel@lsil.com) is senior manager of advanced packaging in the Custom Solutions Technology Marketing group of LSI Logic Corp. (Milpitas, Calif.).