Tom Palkert, Xilinx
Dec 22, 2004 (6:03 AM)
Current state-of-the-art backplanes used on comm equipment designs bundle 1- to 3-Gbit/s lanes to create a 10-Gbit/s connection to support Gigabit Ethernet or Sonet OC-192 traffic. While a good option today, this concatenated lane approach will ultimately give way to the development of a single-lane 10-Gbit/s I/O in order to meet the cost and performance demands of next-generation equipment designs.
This article will look at the design approaches engineers must implement to support the development of a single-lane 10-Gbit I/O. It will also discuss an open-standard simulation tool that will allow designers to better model channel performance when developing single-lane 10-Gbit I/Os
Before looking at the key elements required to develop a single-lane 10-Gbit I/O, let's first address the issue of signaling. Traditionally, in backplane designs, engineers had the option of choosing between PAM and NRZ signaling schemes. While both have their benefits, quite a few companies are leaning toward NRZ because of its scalability, interoperability, and use in many types of interfaces (see sidebar)
The push of NRZ can best be seen in the work being done by the UXPi Group and the Optical Internetworking Forum (OIF). On the OIF front, the PLL working group has formed a projects called the Common Electrical I/O (CEI) , which is defining a signaling scheme for 10-Gbit backplanes using NRZ.
UXPi was formed by a group of companies (IBM, TI, Infineon, AMCC, and Xilinx) to facilitate the interoperability of 10-Gbit interconnects between ASIC, FPGA, and standard products. After examining a number of different signaling techniques, UXPi decided to tap into the work done by OIF's CEI project and, thus, promote the use of standard non-return-to-zero (NRZ) signaling with advanced equalization/signal processing as the best approach to delivering single-lane 10-Gbit connection.
Since NRZ is gaining in popularity among 10-Gbit I/O developers, the recommendations that follow will be for an NRZ-based I/O.
Understanding the Variables The components used in a high-performance backplane interconnect are shown in Figure 1. All of these must be in place to enable the total solution.
Figure 1: Key components needed to develop 10-Gbit backplanes.
There are an almost infinite number of variables in the design of a backplane as shown in Figure 2. The trick is to understand which are the most important and then simulate the entire solution to guarantee performance. Let's look at some of the key variables and some potential solutions to these problems.
Figure 2: diagram showing channel design parameters for single-lane 10-Gbit I/Os.
1. The Transmitter: The transmitter is the beginning of the channel. A good transmitter can do its job to overcome the channel limitations by minimizing its jitter generation, providing pre-emphasis to the launched signal, and minimizing the parasitic elements of the PCB launch. Pre-emphasis puts more signal energy into the high frequency components of the transmit signal to overcome the channel frequency based loss characteristics (Figure 3). If there is a feedback channel from the receiver to the transmitter it is possible to "tune" the pre-emphasis to the channel characteristics.
Figure 3: Diagram showing the impact of pre-emphasis on a transmit signal.
A good signal launch is provided by optimum layout of the die, correct package signal and ground trace routing, and minimum or no vias at the PCB launch point. Usually the package and PCB elements are lumped together and considered a part of the data source (transmitter). Figure 4 shows a schematic of all the parasitic elements that must be accounted for when designing a 10-Gbit/s transmitter.
Figure 4: Diagram showing transmit lunch parasitics.
2. Connectors: Connectors are sources of signal reflections and crosstalk (Figure 5). Minimizing both of these can be done by:
- Avoiding termination techniques which limit backdrilling opportunities.
- Select connector technologies that provide flexibility in positioning via field patterns and allow space for ground isolation vias.
- Minimize via dimensions.
- Maintain impedance tolerance to be less than 10%.
- Using a footprint that permits via-tuning without compromising routing channel space (Figure 6).
Figure 5: Diagram showing the sources of crosstalk.
Click here for Figure 6
Figure 6: Diagram showing the effects of via tuning.
3. Backplane Traces: The traces on the backplane generally account for the longest signal path and contribute the most to the overall loss budget. The backplane design can be improved to support 10-Gbit/s signals by:
- Selection of low-loss laminate materials (Material loss is the dominant effect on long-reach 10Gbps channels) [Figure 7].
- Use wide traces reduce conductor loss (this however increases board thickness).
- Backdrilling is the process by which extra via stubs are removed. This is a small cost adder to the backplane (3 to 5%). Backdrilling tolerance should be maintained within 0.005 in.+/- 0.002 in.
- Use a high aspect ratio for small vias.
- Crosstalk can be reduced by routing signals as differential pairs to provide differential common mode rejection.
Figure 7: Effects of material loss tangent on channel attenuation.
Designers should note that PCB tolerances are sometimes thought to be a major contributor to signal losses. However, losses due to 10% PCB tolerancing are usually minimal in a backplane design.
4. The Receiver: The use of receive equalization allows a channel to operate error free with a closed eye at the receiver. (The eye diagram is open after the signal has passed through the equalizer.) The traditional method of linear equalization attempts to provide signal gain vs. frequency that is inversely proportional to the channel loss vs. frequency response. This method begins to fail when the channel has deep nulls at the Nyquist frequency because the amplifier can generate excess noise.
Decision feedback equalizers (DFEs) were developed to eliminate amplifier noise problems. A DFE looks at the history of the NRZ pulse train and feeds back a signal to compensate for the signal distortions introduced by the channel. The performance of the DFE improves as the number of taps increases allowing designers to tradeoff performance vs power and complexity. As smaller geometry semiconductor processes are used, the power dissipation of the DFE will shrink or additional taps can be added for the same power.
Numerous backplanes have been developed using the solutions to the variables described above. FR4-13, FR4-13SI and R3450 backplane materials have been demonstrated along with Tyco HM-Zd, ERNI 0XT, Winchester SIP and ERNI ERmet-Zd backplane connectors. One demonstration vehicle, which optimized all of the recommendations, is shown in Figure 8 with the associated eye diagram in Figure 9.
Click here for Figure 8
Figure 8: Active test piece design.
Figure 9: Test results without receive equalization.
Note that the test shown in Figures 8 and 9 did not require extensive signal processing at the receiver. This indicates that there is still margin in the design that could be used to support longer distances, cheaper materials, and cheaper connectors.
Possible Advanced Technologies
There are a couple of advanced technologies that designers may also want to consider when developing a single-lane 10-Gbit/s I/O. One method of transmit equalization has been proposed called edge equalization. This technique optimizes the horizontal eye opening at the receiver vs. the traditional method of optimizing the vertical eye. One side benefit of this technique is the ability to transmit both an NRZ and a duo binary eye using the same transmit equalization scheme. This allows designers to choose between a duo binary receiver or a NRZ receiver (Figure 10.
Figure 10: Diagram showing a unified NRZ/Duo binary eye diagram.
Crosstalk cancellation is also being explored. This technique uses a knowledge of both the victim and aggressor signals to cancel the effects of crosstalk in the system.
Electronic dispersion compensation is another possible option. EDC is currently used in optical links to compensate for modal dispersion. It may be possible to apply these same techniques to electrical channels.
One of the biggest challenges in designing a 10-Gbit/s backplane is predicting the system bit error rate (BER) that can be achieved with the specified design parameters. This problem is being addressed by many EDA vendors, but the OIF CEI project has facilitated the development of an open-source software tool, called Stateye, to assist engineers in predicting system operation and measuring the compliance of their channels to required performance specifications.
Stateye uses the underlying mathematical equations that govern S parameter analysis of a channel and creates a time domain eye diagram that can be used to predict the BER performance of a specified channel. Specifically, the Stateye tool allows designers to simulate the effects of:
- Transmit feed forward equalization (FFE)
- Receive FFE and DFE and continuous time equalization
- NRZ and PAM4 signalling methods
- Two-port S-parameters, four-port S-parameters, or ABC parameters can be imported.
- Support crosstalk aggressors
- Multi-mode fiber simulation
The Stateye software was originally developed by Anthony Sanders and Edoardo Prete of Infineon. However, through the help of the OIF, this tool has been expanded. Designers can download the tool at www.stateye.org.
This article has examined the elements required for transmission of data across a backplane interconnect. Each of these elements contributes to the degradation of the transmitted signal.
The article has identified the critical design parameters that should be addressed to allow single-lane transmission of 10-Gbit/s data. These design techniques have been shown to add minimal cost and complexity to the system and if followed should allow backplane designers to "future proof" their systems for single-lane 10-Gbit/s capabilities.
Author's Note: The author would like to thank the Optical Internetworking forum for supporting this article and acknowledge the work of Mike Oltmanns, Northrop Grumman.
About the Author
Tom Palkert is a system architect at Xilinx. Tom is currently involved in standardization efforts at IEEE (Participant in 802.3ap Ethernet over the backplane), INCITS (Vice Chair of T11.2 Fibre Channel), OIF (Former board member Optical Internetworking Forum). He can be reached at email@example.com
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