What platform ASICs are and when to use them

Both are viable paths for implementing complex and high-performance systems on a chip. Determining which solution best fits the application often mixes technical and business considerations. Technical considerations include system performance, logic, and IP (intellectual property) integration requirements. Business concerns typically address product market window, projected volumes, design cost, resources, and risk analysis.

In general, if an application requirement is at the higher end in terms of logic integration (above 5 million ASIC gates), in terms of performance (beyond 300 MHz system performance), and it absolutely has to reach the lowest possible unit cost due to high volume projections, it probably is more suitable for a cell-based ASIC implementation. On the other hand, if time to market and risk mitigation are driving factors, logic integration requirements are around 0.5 million to 5 million gates, and a low barrier of entry outweighs the need for absolute lowest unit cost, then platform ASIC implementation is often the right choice.

Furthermore, these options are not mutually exclusive. An application suitable for a platform ASIC in its initial stages of production may be seamlessly migrated to a cell-based ASIC with similar base technology (silicon and IP) between the two solutions. In this scenario, innovators are given a choice to capture the market with their new product ideas with reasonable upfront investments through platform ASIC and still have a cost reduction path through cell-based ASICs in case the innovation is wildly successful.

What is a platform ASIC?

Since platform ASIC offerings are fairly new to the ASIC market, it is important to define them clearly. A viable platform ASIC solution is a collection of silicon, IP and design methodology tightly defined together, and focused at shortening the design cycle and minimizing development costs for complex systems.

This is done by addressing the areas in the construction of an ASIC which have the greatest impact to the design schedule and its variability. It is important to understand the role each of these three components play in achieving platform ASIC objectives. Platform ASIC silicon typically consists of a group of slices offering different gate ranges, memory, I/O, PLLs and other intellectual property such as high speed Serializer/Deserializers (SerDes). A platform ASIC "slice" is a pre-manufactured device, used to implement a custom system on a chip (SoC).

A slice may be customized through few layers of metal for a user application. An example of a platform ASIC slice is shown in Figure 1. Since only a few layers of metal are customized for any given design, the non-recurring engineering (NRE) costs are significantly lower than a cell-based ASIC development where a full mask set is needed.

Figure 1 — Platform ASIC slice

One of the key contributing factors to shorter design cycles for platform ASICs, in comparison to cell-based ASICs, is design methodology. Platform ASIC users are armed with a head start in their design cycle by starting from a "platform" slice.

Numerous required steps in a cell-based ASIC design flow are typically already completed by a platform ASIC vendor in designing a slice. I/O placement, memory placement and floorplanning, power mesh design, diffused IP clocking and timing, signal integrity analysis and packaging are only a few of these pre-accomplished steps on a slice. So, when the user starts designing with a platform ASIC slice, they actually have considerably fewer steps to complete and hence a shorter design cycle. Another key component of the platform ASIC design methodology relates to the usage of IP. There are typically four different types of IP used in a platform ASIC:

• Diffused IP — Intellectual Property which uses fixed diffusion and metallization using standard cell, custom, and/or mixed-signal logic and its location is non-moveable. The diffused IP may be "paved-over" when not used to recover the routing area and reducing power.
• Hard IP — IP with completed placement and routing using architecture-specific cells. These are moveable, space permitting, since the size and aspect-ratio are fixed. Hard IP is used when control over performance/power limits are required to guarantee performance. An example would be embedding high-end processors such as an ARM926.
• Firm IP — IP which is delivered as a netlist including build deliverables (such as timing constraints, synthesis scripts, simulation models). It may also contain a placement file. Firm IP is used when some control over placement is needed and some flexibility exists or, more often, where RTL code cannot be provided due to contractual obligations.
• Soft IP — IP which is simply delivered as RTL including build deliverables (timing constraints, synthesis scripts). This is simply instantiated and synthesized with the rest of the design. The main advantage of soft RTL is its independence from technology making it easily portable. Higher level SerDes link layer controllers, processor peripherals and specific IP function blocks can all be provided in this manner.

In this case, an application does not need a processor. The Landing Zone area of the die is not wasted and would be available for implementation of other user logic. This Landing Zone flexibility allows a better fit for a slice into multiple applications as an attractive alternative to diffusing the IP and possibly wasting the die area in instances where the IP is not used.

Cell-based ASIC or platform ASIC?

Since platform ASIC users are expected to define their architecture to fit a given target platform (slice), platform ASIC vendors offer families of these slices to fit different applications with various gate, memory, I/O, SerDes and other resource requirements. Having a breadth of options in choosing a platform ASIC slice that best fits an application ensures better cost efficiency and faster design cycle for the end user.

However, if an application's business requirements in terms of piece pricing are extremely stringent, then cell-based ASIC is probably the right solution. Because a cell-based ASIC solution is fully defined to fit its intended application only, it clearly offers maximum cost efficiency.

Many application unit volumes do not justify the full mask set costs required to develop a cell-based ASIC solution. Frequently, these applications tend to have an urgent need to reach the market quickly and possibly are affected by dynamic standards and interfaces, which may change relatively quickly.

Figure 2 shows a typical product volume vs. cost analysis defining the "sweet spot" for both platform ASIC and cell-based ASIC for complex systems on a chip. The crossover product volume point from platform ASIC to cell-based ASIC is fully dependent on the complexity of the design and would differ from one application to another.

Figure 2 — Product volume vs. cost analysis

At the decision point between the choice of platform ASICs and cell-based ASICs, it is important to consider all the factors involved. These factors typically weigh in the final decision to varying degrees:

• Cost analysis (NRE, unit cost, design resources, design tools)
• Technical feasibility of each solution in achieving end-product target features
• Market pressures and the competitive landscape
• Risk analysis
• Engineering resources and project team core competency

For this migration path to be as seamless as possible, choosing a vendor offering both products has significant advantages. An ASIC vendor with both platform and cell-based offerings, using the same base process technology, the same IP and similar methodology between the two solutions can offer a more transparent migration path from platform ASICs to cell-based ASICs.

As the RapidChip Product Marketing Director for LSI Logic, Yousef Khalilollahi is responsible for the "go-to-market" strategy for RapidChip Platform ASIC worldwide. His responsibilities are focused on driving the introduction and market acceptance of LSI Logic's latest innovations in platform ASIC market. Prior to his current role, Yousef had spent 13 years in the FPGA business where he had held various director-level marketing and business development roles at Actel Corporation.