Much has been made of the vision of a "single-chip phone" that leverages industry-standard process technologies and historical silicon integration trends to consolidate handset functionality on a die. But in cell phones and other wireless products, where equal parts analog/RF, digital and mixed-signal must all work together to achieve a system solution, it's not as straightforward a proposition. Nevertheless, the industry has made great strides in continuing to implement all of the functional handset blocks in a very small number of devices. Now we appear poised to achieve a long-awaited system-on-chip handset. But there is deliberation over what this means, if it makes sense and the best way to get there.
Let's get semantics out of the way. While single-chip implies that the bulk of the mobile-phone functionality is on one chip, the degree of integration remains open to interpretation. Some might see the chip including a high level of integration within the digital/baseband domain or within the RF space, greatly simplifying product design. To others, single-chip implies a broader approach that would combine the RF, analog and baseband portions, and perhaps even RF power and switching, on a single device .
Contrast that with system-in-package (SiP), where dice produced with different process technologies can be integrated in a high-density solution at the package level. SiP can yield such products as matched power amplifiers, RF front-end transmit chains or even single-package radios, all of which exist today. Furthermore, the SiP idea can be extended to include all mixed-signal and digital functions.
Thus, SoC and SiP should be viewed more as processes or trends than as end states. The reality is that cost pressures and technology advances are significant drivers and that integration will continue to occur, simplifying the bill of material at the handset level for a given function, regardless of the approach. The "right" mix of SiP and SoC will be depend on numerous factors, including the functionality and customization levels demanded in various market segments, further commoditization of the handset electronic backbone, the availability of broadly capable technologies and, most critically, the cost implications.
The tremendous growth in handset features has changed the design and marketing of mobile phones, resulting in a dramatic expansion of design content supporting peripheral functions, such as digital cameras, multimedia and enhanced user interfaces. This trend, combined with the migration to advanced communication standards, such as 3G, drives the "tiering" of handset products. Feature-rich offerings command a breadth of technical capabilities, but they also require rapid time-to-market, uncompromised performance and a high level of customization, as well as low cost. These demands will continue to dictate a need for flexibility in design and the ability to match subsystem components and devices for optimum cost vs. performance. This favors a discrete-component or SiP approach across the system partitioning, acknowledging that integration will continue to evolve in the core devices.
At the same time, a lower-tier market segment exists that focuses on the core mobile-phone functionality and on the few advanced features that have become highly standardized and commoditized. Increasingly, these designs would require little or no hardware customization at the system level across handset platforms. This segment enables opportunities for more-encompassing SoC devices. Highly integrated solutions in high-volume, standardized devices can offset the higher development costs and longer lead times at the device level, offering a more rapid design cycle at the system level. The assumption is that the selected partitioning and the SoC technical solution are capable of achieving an adequate level of performance, at a lower cost than for the discrete solution.
The ability to integrate many functions into a system-on-chip has been demonstrated in the digital and RF realms. For example, transceiver solutions that integrate previously discrete devices-such as the receiver, transmitter, voltage-controlled oscillator and low-noise amplifiers-into a very small, cost-effective device have already proved commercially successful. Similar achievements have been prominent in the baseband. This trend will continue and will be successful if optimized integration goals are targeted.
A highly aggressive approach toward integrating radio and baseband elements into an SoC device would likely also be technically possible, but here the cost implications would be a challenge. The road map for CMOS processes provides an aggressive cost-reduction path for digital circuits. But RF and analog circuits and passive components, which will constitute a large percentage of the device area, will not scale linearly at the finer geometries, and their performance requirements may cause substantial customization of the silicon fabrication process.
This combination can limit the cost benefits of integrating on a CMOS platform and may result in a higher cost than a discrete or SiP solution because of higher wafer costs and larger, lower-yielding dice. Indeed, this dynamic is not unique to the mobile-handset design space; integration in far more mature electronic products has stopped short of full integration for the same reason.
Achieving continued improved performance in a standardized SoC process creates challenges in the RF blocks and certainly in the RF front end. While it is possible to achieve power consumption parity between RF-CMOS solutions and specialty process technologies like Bi-CMOS or silicon germanium, such parity is significantly more difficult to achieve with CMOS-based designs because of the challenges associated with achieving high gain and controlling close-in 1/f noise.
These problems often precipitate more design iterations and may limit performance in demanding radio applications, such as 3G.
These challenges will likely ultimately be addressed, but for now they remain significant. In the front end, many circuits, including power amplifiers, RF switches, large-value passives and precision RF filters, do not leverage the capabilities of high-volume silicon processes in terms of feature size reduction or high-mask-count processes and, in some instances, are simply just not process-compatible. In addition, continued performance and cost improvements in the discrete forms of these devices continue to raise system designers' expectations, compounding the challenge.
So, what does this mean? Market and function segments exist for both SoC and SiP integration, and the approaches should be viewed as complementary rather than competitive. Designers will continue to leverage the strengths of systems-on-chip in standardized processes for digital-centric functions, driving further integration of additional functions when it makes technical and business sense to do so. SiP, for its part, will be a workhorse approach in functional blocks that take advantage of a mix of devices and components to maximize performance and cost, most clearly in the RF front end. Designers will thus be able to develop products well in front of the silicon integration curve.
Clearly, SoC will continue to evolve through innovationv providing opportunities for cost reduction and system design simplification, including integration of some radio elements into the baseband over time. But companies that remain unbiased and well-versed in the appropriate use of both approaches, in the appropriate context, will be positioned to make the best choices today and in the future.
Steve Machuga (firstname.lastname@example.org), vice president of technology development at Skyworks Inc. (Woburn, Mass.)