D&R Industry Articles

Articles for the Week of April 28, 2025

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Optimizing 16-Bit Unsigned Multipliers with Reversible Logic Gates for an Enhanced Performance

Articles for the Week of April 21, 2025

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Automating Hardware-Software Consistency in Complex SoCs

Engineering teams must coordinate across hardware and software domains as system-on-chip (SoC) designs scale in complexity. Designers must verify that register definitions remain accurate and synchronized throughout the development cycle.

• How NoC architecture solves MCU design challenges

Articles for the Week of April 14, 2025

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Beyond Limits: Unleashing the 10.7 Gbps LPDDR5X Subsystem

The rapid growth of mobile computing, AI, and Automotive technologies is driving demand for faster, more efficient, and highly reliable memory with higher capacity

• How to Design Secure SoCs: Essential Security Features for Digital Designers

Articles for the Week of April 7, 2025

• System level on-chip monitoring and analytics with Tessent Embedded Analytics

Articles for the Week of March 31, 2025

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What tamper detection IP brings to SoC designs

The growing complexity and frequency of security threats facing organizations across the globe has transformed opinion about what’s needed to keep devices secure. Modern system-on-chips (SoCs) take a ‘Zero Trust’ approach, assuming that no user, device or application is inherently trustworthy. In parallel to this approach, complementary solutions, including anti-tamper measures, are increasingly importan

• RISC-V in 2025: Progress, Challenges,and What's Next for Automotive & OpenHardware

Articles for the Week of March 24, 2025

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Understanding MACsec and Its Integration

MACsec, as defined by the IEEE 802.1AE standard, provides protection for traffic passing over Layer 1 and Layer 2 links. It is designed to prevent a range of security threats, including man-in-the-middle attacks, pasive wiretapping, impersonation, and replay attacks. By applying protection at the data link layer, MACsec ensures that all communication between devices on the same network segment is secure.

• Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.

Articles for the Week of March 10, 2025

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Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency

This paper aims to provide a comprehensive understanding of density issues, and the methodologies used to perform effective density checks in VLSI layout design.

• The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know

Articles for the Week of March 3, 2025

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How the Ability to Manage Register Specifications Helps You Create More Competitive Products

The semiconductors business is incredibly competitive, with dynamic end markets and constant shifts in leading products and vendors. It takes excellence on many fronts to succeed, far more than I can cover in a single blog post. Thus, I’m going to focus on one particular aspect of developing competitive IP and system-on-chip (SoC) products: the ability to manage your register specifications and automate the process of turning them into silicon.

• Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation

Articles for the Week of February 24, 2025

• EAVS - Electra IC Advanced Verification Suite for RISC-V Cores

Articles for the Week of February 17, 2025

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Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices

In this blog post, we shall explore the methodology of 3D reconstruction on the multi-view object scenes, used for volumetric object dimensioning in autonomous robots. We shall also detail the steps of capturing data streams, generating object point clouds, reconstructing 3D point clouds through local and global registration algorithms, and calculating object dimensions in 3D. The results will be presented at the end.

• Why RISC-V is a viable option for safety-critical applications

Articles for the Week of February 10, 2025

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Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World

Quantum computing advances are exciting, but they’re also a looming threat to securing ICs, driving the need for Post-Quantum Cryptography (PQC). Learn about PQC, how it’s being implemented, and the legislation involved.

• What is JESD204B? Quick summary of the standard

Articles for the Week of February 3, 2025

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Analysis and Summary on Clock Generator Circuits and PLL Design

The demand for analog and mixed-signal-based integrated circuits (ICs) has surged due to the increasing reliance on electronic-based applications across industries. As the world transitions to more advanced technologies, low-noise, low-power systems have become highly competitive in achieving optimal design performance. Among the most critical components are clock generator circuits, which require low phase noise and low jitter for high-precision operation.

• Understanding why power management IP is so important
• Hardware-Assisted Verification: The Real Story Behind Capacity