D&R Industry Articles
Articles for the Week of July 22, 2024
![Rising respins and need for re-evaluation of chip design strategies](http://static.designandreuse.com/news_img2/news56562/150x102-s.jpg.webp)
Rising respins and need for re-evaluation of chip design strategies
As a result of design complexity and market competition, innovative chip development strategies have become essential for expedited market entry and revenue growth. Tapping into these technological advances is a strategic imperative to secure market leadership.- Simplifying analog and mixed-signal design integration
- AI-driven SRAM demand needs integrated repair and security
Articles for the Week of July 8, 2024
![Select the Right Microcontroller IP for Your High-Integrity SoCs](http://static.designandreuse.com/news_img2/news56485/150x102-e.jpg.webp)
Select the Right Microcontroller IP for Your High-Integrity SoCs
There may be a seemingly unlimited array of microcontrollers for consideration, but how do you select the right one when developing high-integrity SoCs that meet all functional-safety requirements?Articles for the Week of July 1, 2024
![Optimal OTP for Advanced Node and Emerging Applications](http://static.designandreuse.com/news_img2/news56473/150x102-e2.jpg.webp)
Optimal OTP for Advanced Node and Emerging Applications
While leading foundries keep pushing Moore’s law to the limit of physics, embedded non-volatile memory (eNVM) is becoming a game-changer in designing advanced integrated chips.Articles for the Week of June 17, 2024
![Creating SoC Designs Better and Faster With Integration Automation](http://static.designandreuse.com/news_img2/news56398/150x102-a.jpg.webp)
Creating SoC Designs Better and Faster With Integration Automation
A modern high-end system-on-chip (SoC) design can be extremely large and enormously complex, employing thousands of intellectual property (IP) blocks. Most of these IPs will be sourced from trusted third-party vendors. These will typically be augmented by one or more internally-developed IPs to provide the secret sauce that will distinguish this SoC from its competitors.Articles for the Week of June 10, 2024
![System-on-chip (SoC) design is all about IP management](http://static.designandreuse.com/news_img2/news56368/150x102-f.jpg.webp)
System-on-chip (SoC) design is all about IP management
For most system-on-chip (SoC) designs, the most critical task is not RTL coding or even creating the chip architecture. Today, SoCs are designed primarily by assembling various silicon intellectual property (IP) blocks from multiple vendors. This makes managing silicon IP the dominant task in the design process.- Shift Left for More Efficient Block Design and Chip Integration
- Certifying RISC-V: Industry Moves to Achieve RISC-V Core Quality
- Speeding Derivative SoC Designs With Networks-on-Chips
Articles for the Week of June 3, 2024
![Procrastination Is All You Need: Exponent Indexed Accumulators for Floating Point, Posits and Logarithmic Numbers](http://static.designandreuse.com/news_img2/news56303/150x102-o.jpg.webp)
Procrastination Is All You Need: Exponent Indexed Accumulators for Floating Point, Posits and Logarithmic Numbers
This paper discusses a simple and effective method for the summation of long sequences of floating point numbers. The method comprises two phases: an accumulation phase where the mantissas of the floating point numbers are added to accumulators indexed by the exponents and a reconstruction phase where the actual summation result is finalised.Articles for the Week of May 27, 2024
![Using PSS and UVM Register Models to Verify SoC Integration](http://static.designandreuse.com/news_img2/news56272/150x102-a.jpg.webp)
Using PSS and UVM Register Models to Verify SoC Integration
One particularly challenging stage of SoC development is verifying that the complete design has been assembled correctly. This requires checking to be sure that both the software and hardware do what they are intended to do. Automating much of this process is possible using a combination of the Portable Stimulus Standard (PSS) and Universal Verification Methodology (UVM) register models.Articles for the Week of May 20, 2024
![Why verification matters in network-on-chip (NoC) design](http://static.designandreuse.com/news_img2/news56248/150x102-a.jpg.webp)
Why verification matters in network-on-chip (NoC) design
In this article, we will dive deeper into a comprehensive methodology for formally verifying an NoC, showcasing the approaches and techniques that ensure our NoC designs are robust, efficient, and ready to meet the challenges of modern computing environments.- Temperature Sensors for ASICs
- How control electronics can help scale quantum computers
- Functional Safety for Control and Status Registers
Articles for the Week of May 13, 2024
![An Introduction to Post-Quantum Cryptography Algorithms](http://static.designandreuse.com/news_img2/news56230/150x102-e.jpg.webp)
An Introduction to Post-Quantum Cryptography Algorithms
The rise of quantum computing paints a significant challenge for the cryptography we rely on today.Articles for the Week of May 6, 2024
Additional ArticlesArticles for the Week of April 29, 2024
![Synopsys 3DIO Solution for Multi-Die Integration (2.5D/3D)](http://static.designandreuse.com/news_img2/news56164/150x102-s.jpg.webp)
Synopsys 3DIO Solution for Multi-Die Integration (2.5D/3D)
The demand for high performance computing, next-gen servers, and AI accelerators is growing rapidly, increasing the need for faster data processing with expanding workloads.