LDO Voltage Regulator, 30 mA, Adjustable 0.45 V to 0.9 V Output
D&R Industry Articles (March 2003)
Articles for the Week of March 31, 2003
Additional ArticlesArticles for the Week of March 24, 2003
Additional Articles- Why you need RTL virtual prototyping
- Reusable Verification Infrastructure for A Processor Platform to deliver fast SOC development
- SoC testing becomes a challenge
- Bluetooth needs advanced subsystem IP
- When IP test becomes test IP
- Design reuse expands across industry
- Designing 5-Gbit/s Serdes: Steering Through a Road Filled with Potholes
- Diagnostics for Design Validation
- Using PLLs to Obtain Carrier Synchronization
- ISQED speakers back platform-based design
- Hierarchy Management for Million Plus Gate Counts
Articles for the Week of March 17, 2003
Additional Articles- Using Memory More Effectively in NPU Designs
- Simple techniques for making verification reusable
- Ultrawideband and WiMedia
- Programmable systems are the next 'killer app'
- Process experts map path to 90-nm memory
- Yield-raising methodology closes loop between design, manufacturing
- Mobile generation needs FRAM
- Merged-logic-type embedded DRAM suits high-performance SoCs
- Nonvolatile memories for 90nm SoC and beyond
- Speed with flexible design critical to embedded DRAM for SoCs
- Manufacturability, scalability: a critical test of SoC memories strategies
- Transaction-level models eyed as SoC enabler
Articles for the Week of March 10, 2003
Additional Articles- An IP-based SoC Design Kit for Rapid Time-to-Market
- 8- and 16-bit processors: state of the art
- Prototyping ARM926 PrimeXsys-based SoCs
- Combined coverage methodology speeds verification
- SoCs' death somewhat exaggerated: panel
- Reusability and Modularity in SoC Verification
- Chip Design - better asynchronous than synchronous?
- Security at the edge challenges TCP/IP, WLAN infrastructure
Articles for the Week of March 3, 2003
Additional Articles- The case for SystemC
- Statistical techniques attack process variation
- What designers need to know about structural test
- Executable SystemC environment will drive ESL adoption
- DFT: A systems technology for system chips
- Pre-configured DFT structures can simplify ASIC design, verification
- Shifting from functional to structured techniques improves test quality
- Moving DFT to RTL overcomes test vector issues
- Linking synthesis with DFT key for network switch ICs
- Analog circuits need more than just DFT methods