This paper explains how, in our endeavor to accomplish an ideal verification platform for our designs using System Verilog and a standard methodology(OVM) plus some in-house ideas over it, helped us to make a more practical and easy to use verification environment.
Design reuse is usually performed on a small scale in analog design. Proven design topologies and concepts are recycled by duplication, modification and development during conversion. A lot of repeated manual and interactive tasks dominate the process to transfer the design data between technologies. Hence tool support to reduce failures during conversion is necessary. We present an approach to convert a circuit design from technology A to technology B. It is separated into topology conversion to transfer design data and an optimization step for sizing.