D&R Industry Articles (February 2010)
Articles for the Week of February 22, 2010Additional Articles
- Software Architecture for IP verification in Operating System environment
- High-level synthesis, verification and language
- Analog and Mixed Signal Modeling Approaches
Articles for the Week of February 15, 2010
Traffic Management for Optimizing Media-Intensive SoCsThe drive to constrain product costs and power consumption places severe limits on system designers, particularly with external memory bandwidth. To increase performance, designers need to focus on efficient use of this system bandwidth. In turn, this drives the need for products to help with the analysis of the system dynamics and intelligent fabric architectures to manage the scarce resources. This article examines the role of Verification and Performance Exploration (VPE) and introduces the design objectives behind the advanced Quality-of-Service (QoS) mechanisms to optimize the performance that can be delivered by such systems.
- Reusable VHDL IP in the Real World
- My FPGA's not working: Problems with the IP
- Guidelines for complex SoC verification
Articles for the Week of February 8, 2010
Improving Software Development and Verification Productivity Using Intellectual Property (IP) Based System PrototypingOnce a chip development project has started, project managers are asked almost immediately to provide early representations of the chip development for various purposes. This paper will review different use models driving requirements for intellectual property (IP) models in different project stages. Different prototyping techniques will be introduced and we will outline that none of them alone is able to meet all requirements users have for IP models.
- Re-Configurable Platform for Design, Verification and Implementation of SoCs (Design and Verification without Constraints)
- Partitioning an ASIC design into multiple FPGAs
- A Formal Methods-based verification approach to medical device software analysis
- Managing Complex SoC verification using plan based verification techniques
- Reducing Costs, Risks, Time to Market with Virtualized Systems Development
Articles for the Week of February 1, 2010
Module Threading Technique to Improve DRAM Power and PerformanceThis paper provides details of all DRAM timing constraints which have heavy impact on memory system performance and introduces module threading technique to overcome these limitations. It also provides detailed theoretical analysis on how module threading can offer finer granularity, higher bandwidth and importantly lower power consumption. It also provides board level analysis where 25% power was saved and a higher performance achieved by adopting module threading technique.
- Arrgghh! My FPGA's not working: Problems with the RTL
- Viewpoint: Formal verification with constraints - It doesn't have to be like tightrope walking
- Increasing bandwidth in industrial applications with FPGA co-processors
- Embedded system virtualization for executable specifications and use case modeling