32G LR Multi-Protocol SerDes (MPS) PHY - GLOBALFOUNDRIES 22nm
D&R Industry Articles (May 2010)
Articles for the Week of May 31, 2010
Breaking the 2 Giga Access Barrier: Overcoming Limited I/O Pin Counts
Cisco’s Visual Networking Index forecasts that the Internet growth will quadruple by 2013. Projected Internet traffic will approach 1 Zettabyte (1 trillion Gigabytes) per year. To support this amazing trend, the next generations of networking equipment must offer new levels of packet forwarding rates and bandwidth density. This in turn will necessitate new generations of packet processors and the memory subsystems to support these increased demands. MoSys is stepping up to this challenge by introducing a new class of device to accelerate access to packet forwarding information, statistics calculations and packet storage.Articles for the Week of May 24, 2010
Additional Articles- What is power debugging?
- Code coverage convergence in configurable IP
- Selecting the right Nonvolatile Memory IP: Applications and Alternatives
- The 'off-the-shelf' IPs for today's SoCs
- A designer's guide to a new industrial control paradigm
- Mixed-signal and power-integration packaging solutions
Articles for the Week of May 17, 2010
Continuous integration of complex reconfigurable systems
This paper elaborates on the advantages of continuous integration for FPGA SoC projects, reports on real-world usage of CI for the design of a scalable video decoder and provides some guidelines for setting up a new continuous integration system.- Protecting FPGAs from power analysis security vulnerabilities
- H.264 High Profile: Codec for Broadcast & Professional Video Application
- Current thoughts on custom IC design
Articles for the Week of May 10, 2010
A RTCA-DO-254 Compliant Development Process for Supporting the Design of High-Quality Hard IP Cores
The increasing structural complexity and the decreasing size of integrated circuits, associated with the reduction on design time, demands that the hardware designer uses a very well planned design flow to obtain high quality IP-cores. With increasing demand on more complex IP-cores, mechanisms for guaranteeing the design quality are being standardized and must be included in the design flow. The DO-254 standard is an example of such standardization for airborne systems.- Using unified modeling methods to reduce embedded hardware/software development
- Algorithmic delay and synchronization in MPEG audio codecs
- Powering Down: Enabling a Power Regression Flow for SoC Design
Articles for the Week of May 3, 2010
DDGEN: An Automated Device Driver Generation Tool for Embedded Systems
This paper describes a methodology for automatically generating device drivers for embedded systems. We formally specify the device behavior and attributes in an input specification called DPS (Device programming sequence). Software architecture considerations are similarly captured in another specification called RTS (Run time specification). Our tool, DDGEN takes both these specifications as input and generates a full-fledged device driver code for the target operating system.- The Need for Variable Precision DSP Architecture
- A Novel Mesh Architecture for On-Chip Networks
- The documentation challenge
- Integrating analog video interface IP into SoCs delivers superb image quality (Part II)