This paper discusses the class of virtual platforms called host simulations. With host simulation, the embedded application code is compiled for the host processor using native compilers and executed directly on the host machine. This paper presents the characteristics of reusable device simulation models, and the methods to design and implement them. It also discusses the steps required to execute an embedded application code on a host machine using host simulation.
Physical designers moving to lower foundry nodes worry about how to verify and deliver a design that is free of DRC violations while meeting their tape-out schedule. This can be quite challenging given that the number and complexity of DRC rules is increasing and designs are getting bigger. The need for a better understanding of the manufacturing issues during the design phase raises concerns about how to best address these issues.