D&R Industry Articles (April 2012)
Articles for the Week of April 30, 2012
A Digital Design Flow for Differential ECL High Speed Applications
This paper presents a digital design flow in order to design high performance differential Emitter Coupled Logic (ECL) circuits efficiently. The proposed flow is similar to the ordinary digital CMOS Design Flow. It uses standard design tools for gate-level synthesis and layout generation. The differential logic synthesis is separated in two phases. Starting from a synthesized, single-ended HDL design description, a fully differential ECL netlist is generated using a Verilog netlist converter before the layout phase. This results in a short development time and fast verification possibilities. Furthermore, the layout generation can be done in one shot together with digital CMOS components.- Hierarchical methods for power intent specification
- Processor Optimization Pack (POP) Solutions: Enabling the Fastest Design Closure of Your ARM Cortex-A9 Processor
- A modeling approach for power integrity simulation in 3D-IC designs
Articles for the Week of April 23, 2012
The Challenge of the Clock Domain Crossing verification in DO-254
In order to meet high-performance and low-power requirements, FPGA and ASIC designs often include many separate clock domains. This practice creates Clock Domain Crossing (CDC), which occurs whenever a signal is transferred from a clock domain to another. However, these signals may cause data corruption issues, only occurring during post-layout verification, because conventional RTL verification techniques cannot detect resynchronization problems. As a consequence, critical bugs may escape the verification process and simulation does not accurately predict asynchronous silicon behavior.Articles for the Week of April 16, 2012
Enabling High Performance SoCs Through Multi-Die Re-use
This paper gives a high-level overview of a technique for rapid design of new IC designs using multiple dice packaged in a variety of aggregations allowing for differnent performance levels and price points to be achieved. The technique relies on a new high-bandwidth low pin-count communication channel between two or more dice.- Design for power methodology
- Managing the coming explosion of embedded multicore virtualization
- Low power is everywhere
- Design considerations for power sensitive embedded devices
- Building predictability into your low-power design flow
- Embedded 3D graphics is here, but 2D is still important: Here's why
Articles for the Week of April 9, 2012
Which USB is right for your application? (Part 3)
In 2007, I wrote a two-part series titled “Which USB is Right for your Application” for Planet Analog (Part 1 and Part 2). Since then, several new and different “versions” of USB have been released. In this article, I discuss how they have been deployed in the market in the almost five years since.- SoC low-power verification requires a full-chip solution
- Boost MCU security AND performance with hardware accelerated crypto
- "Early and accurate" power analysis: myth or reality?
- Automatic C-to-VHDL testbench generation shortens FPGA development time
- Tips for testing processor cores
- 2D vs. 2.5D vs. 3D ICs 101
- Considerations for writing UPF for a hierarchical flow
Articles for the Week of April 2, 2012
Encoding H.264 without External DRAM : Power and Quality Comparison
This article compares the power consumption and quality of the generated bitstream between two Ocean Logic H.264 encoder cores : OL_H264E that uses external DRAM to store the reference frame store and OL_H264E_CFS that uses a Compressed Frame Store (CFS) technology that does not need external DRAM.- Inside the Xilinx Kintex-7 FPGA: A closer look at the first FPGA to use HKMG technology
- Opinion: Challenges and techniques to meet power budget in complex systems
- Overcome signal attenuation, noise and jitter interference challenges in USB 3.0 system design
- Optimizing performance, power, and area in SoC designs using MIPS multi-threaded processors
- Efficient C code for ARM devices