MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
D&R Industry Articles (May 2012)
Articles for the Week of May 28, 2012
Analog IP Nirvana: a modular based design methodology for addressing the agility
In this paper we propose a modular design methodology which can handle the agility of analog IP and help to achieve the first pass silicon. A case on PLL design will be discussed to highlight the key benefit of this design methodology.- Designing embedded SoCs using older resistive technologies
- Using emulation to debug software and hardware at the same time
- Beat power management challenges in advanced LTE smartphones
- System-level design of mixed-signal ASICs using simulink: Efficient transitions to EDA environments
- Accelerate partial reconfiguration with a 100% hardware solution
Articles for the Week of May 21, 2012
AMBA 4 ACE for Heterogeneous Multiprocessing SoCs
AMBA 4 ACE adds system-level coherency support to the AMBA 4 specifications. By enabling cache coherency between the high- performance ARM Cortex-A15 MPCore processor and software-compatible high- efficiency Cortex-A7 MPCore processor it enables energy savings through heterogeneous multiprocessing, termed ‘big.LITTLE’ by ARM.- Implementing SPI on an OMAP-based board design
- Power: a significant challenge in EDA design
- FPGA testing for DO-254 compliance
- A scalable, cost-effective phase change RAM technology
- Applications and Use of Stage-based OCV
Articles for the Week of May 14, 2012
3D IC 2-tier 16PE Multiprocessor with 3D NoC Architecture Based on Tezzaron Technology
In this paper, we describe the design flow, architecture and implementation of our 3D multiprocessor with NoC. The design based on 16 processors communicating using a 4x2x2 mesh NoC spread on two tiers is discussed in detail and will be fabricated using Tezzaron technology with 130 nm Global Foundaries low power standard library. The purpose of this work is to accurately measure NoC performances in real 3D chip when running mobile multimedia applications to evaluate the impact of 3D architecture compared to 2D.- The growing use of programmable logic in mobile handsets
- Reducing energy cost of intra-chip communications
- Top 10 Tips for Success with Formal Analysis - Part 3
- How to use the CORDIC algorithm in your FPGA design
Articles for the Week of May 7, 2012
Channel Core Flex: An Advanced Channeliser for Next Generation Digital Radio Receivers
This paper discusses the relative merits of the various digital signal processing techniques used to channelise signals. ChannelCore Flex (CCF) exploits all of these strengths to provide a flexible channeliser architecture that is capable of supporting thousands of independently defined channels in a single FPGA. The CCF core can be tailored at build-time to support the user’s generic channel plan and required level of flexibility. The precise channel plan can then be loaded and updated at run-time. The FPGA resources required to implement CCF in a Xilinx Spartan-6 LX100 are presented for an example channel plan with 1024 channels of various bandwidths.- Interconnect modeling at 20nm - more of the same or completely different?
- Landscape for board design changes beyond 10G
- Using GPUs to accelerate EDA applications
- How secure is AES against brute force attacks?
- Enough of the sideshows - it's time for some real advancement in functional verification!
- New generation RISC processing power - Green technology engenders new business opportunities
- Design for reliability - the golden age of simulation driven product design
- Time is money! A quick fix for those pesky FPGA design errors
Articles for the Week of April 30, 2012
Additional Articles- Troubleshoot and verify 8b/10b encoded signals with a real-time oscilloscope
- Lessons in developing and deploying OVM Compliant VIP