Today semiconductor industry are more emphasizing on the die size reduction and less metal layers technology process options to improve gross margins but as we are decreasing more and more die size, design needs to be closed at higher utilization. Closing the highly utilized design with lesser metal layers option will end up in routing congestion, higher cross talk noise, worsen IR drop. In this paper we propose the novel non-orthogonal metal layer concept in power distribution network for SOC’s.
In this paper, we outline the various parameters that affect the memory sub-system performance and also introduce the Sensitivity Analysis and Feature Exploration methodologies to analyze the degree of impact of each of these parameters. This platform, when used at an early architectural exploration phase, provides valuable feedback to the memory device, controller and PHY architects to focus on optimizing the most critical parameters. We present a case-study to analyze a next generation mobile DRAM based memory sub-system using our proposed performance architectural exploration platform, and provide a ranking metric for all the parameters that affect the memory sub-system performance for key mobile applications.