Configurable controllers for PCIe 4.0 and CCIX supporting Dual Mode applications
D&R Industry Articles (May 2014)
Articles for the Week of May 26, 2014
CPF Based Verification of an SoC - Lessons Learnt
Power Management keeps being a very valuable asset for mobile applications. CPF (Common Power Format) is a common file format to describe the power structure of the design in the early design stages that makes it a very critical design step input of the VLSI design flow. It is possible to verify a design from low power point of view using lint tools and/or simulations without CPF, but not as effective as a CPF based simulation methodology.- Implementing Floating-Point Algorithms in Real Hardware: Remember the Adaptation Step
- IoT Security
- Rail analysis for SoC ASICs
- Dealing with automotive software complexity with virtual prototyping - Part 3: Embedded software testing
- Dealing with automotive software complexity with virtual prototyping - Part 2: An AUTOSAR use case
- Dealing with automotive software complexity with virtual prototyping - Part 1: Virtual HIL development basics
Articles for the Week of May 19, 2014
Design Rights Management of Intellectual Property (IP) Cores in SoPC designs
This paper presents a Design Rights Management methodology used in a practical EDA tool suite: IP-Idol, developed by the start-up Algodone, based in Montpellier-France. It consists to encrypt and decrypt Hardware Description Language models (following IEEE 1735 and part of IEEE 1800 standards) of some Intellectual Property Cores (IP) in SoPC (System on Programmable Chip) with a strategy model where Algodone plays the role of a trusted third party.- Overcoming advanced SoC routing congestion with 2.5D system in packaging
- Performance optimization using smart memory controllers, Part 1
Articles for the Week of May 12, 2014
Tradeoffs of LDO Architectures and the Advantages of Advanced Architecture "Capless" LDOs
Power management of battery-powered electronic devices is becoming increasingly more important for the present and future microelectronics industry. This application note details the difference between low dropout (LDO) voltage regulators that use output capacitance and those that do not and how your system designs can benefit from or be improved by not using an output capacitor.- Optimizing embedded software for power efficiency: Part 4 - Peripheral and algorithmic optimization
- Optimizing embedded software for power efficiency: Part 3 - Optimizing data flow and memory
- Optimizing embedded software for power efficiency: Part 2 - Minimizing hardware power
- Optimizing embedded software for power efficiency: Part 1 - measuring power
Articles for the Week of May 5, 2014
Auto Clock Generation in a SoC
This paper discusses a novel idea on automatic clocks generation for a SoC. A standard configurable input file has all the required clock requirements in a SoC given by the designer. A scripting language is used to parse the input file. The script generates Synthesizable System Verilog RTL, System Verilog Assertions, Clock Constraints and Documentation in HTML format.- An alternative to ADC, power and RF IC hardware: the S3 Group
- Heterogeneous Computing Meets the Data Center