D&R Industry Articles (June 2016)
Articles for the Week of June 27, 2016
Additional ArticlesArticles for the Week of June 20, 2016
Easing Heterogeneous Cache Coherent SoC Design using Arteris' Ncore Interconnect
Heterogeneous processing has become a hallmark of mobile SoCs, but designing cache coherency across these diverse processing elements can be difficult. Standard on-chip interfaces and network-on-a-chip (NoC) technology are the first step, giving architects IP to efficiently connect compute processing elements as different as CPUs, GPUs, and DSPs. Hardware IP to enable coherent communication between different types of compute engines is the next step. This white paper describes how Arteris’ Ncore IP can help architects design processors fully supporting coherency between heterogeneous elements.Articles for the Week of June 13, 2016
Fronthaul Evolution Toward 5G: Standards and Proof of Concepts
This paper will help to navigate through the key concepts of packet based Fronthaul and discuss the implications of the adoption of latest Time-Sensitive-Network (TSN) IEEE 802.1CM standard, the IEEE P1904.3 Radio over Ethernet (RoE) standard and latest Next Generation Fronthaul Interface, (NGFI) IEEE P1914.1 initiatives. Finally, a look at the PoC platforms enabled by Xilinx technology and IP offering from Comcores will be offered.- What's in the Future for High-Speed SerDes?
- Thorough validation: the conundrum of Pulsed latch libraries turned practical as Spinner systems
Articles for the Week of June 6, 2016
Lossless Medical Video Compression Using HEVC
This paper outlines lossless encoding mode of HEVC and how using lossless encoding mode, compression ratio of more than 2 (2:1) can be achieved.Articles for the Week of May 30, 2016
Additional Articles