MIPI C-PHY v1.2 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (16nm) for Automotive
D&R Industry Articles (November 2017)
Articles for the Week of November 27, 2017
Resolution of Interoperability challenges in Automatic Test Point insertion across different EDA vendors
For a typical design there may be some design corners where ATPG tool/algorithm may find hard to generate patterns for fault detection. This leads to loss of coverage or increase in pattern count. To overcome this issue EDA tools(DFT/ATPG) provide options to insert Control logic on locations/nodes with poor controllability or Observe test logic on locations/nodes with poor observability, these are referred as Test Points.- Dynamic Margining: The Minima Approach to Near-threshold Design
- IPs for automotive application - Functional Safety and Reliability
Articles for the Week of November 20, 2017
Additional ArticlesArticles for the Week of November 13, 2017
eFPGA IP Density, Portability & Scalability
There are multiple eFPGA suppliers in the market today: Achronix, Adicsys, Efinix, Flex Logix™, Menta, QuickLogic. There are 3 different business models and engineering approaches to eFPGA which you should understand to assess how it will impact your success in using their eFPGA IP and their viability as a supplier long term.- Securing IoT Devices can be Never-Ending
- Why is Analog increasingly important in the Digital Era?
- Overcoming Timing Closure Issues in Wide Interface DDR, HBM and ONFI Subsystems
Articles for the Week of November 6, 2017
Ins and Outs of Assertion in Mixed Signal Verification
In this article, we demonstrate how the mixed signal assertions are different from digital assertions and how an assertion-based Verification (ABV) is extended to the Mixed Signal verification. This article also covers different assertion techniques in Mixed-Signal Verification Systems.