Evatronix S.A - Articles

≡ Menu Design And Reuse

Design And Reuse


D&R Industry Articles \| Most Popular \| SoC News Alerts \|

Evatronix S.A

Title Sign Up for SoC News Alert	Publication


Long live the battery!	Mar. 04, 2013

Secure Mobile Payments - Protecting display data in TrustZone-enabled SoCs with the Evatronix PANTA Family of Display Processors	Nov. 05, 2012

SystemC library supporting OVM compliant verification methodology	Sep. 10, 2012

Software generated BCH as a way to solve challenges of providing multiple configuration IP	Mar. 05, 2012

NAND Flash memory in embedded systems	Sep. 29, 2011

USB3.0 application building using low performance 8-bit microcontroller	Sep. 06, 2011

Systematic approach to verification of a mixed signal IP - HSIC PHY case study	Apr. 21, 2011

Verification of USB 3.0 Device IP Core in Multi-Layer SystemC Verification Environment	Mar. 17, 2011

Hardware Solutions to the Challenges of Multimedia IP Functional Verification	Feb. 14, 2011

The 'off-the-shelf' IPs for today's SoCs	May. 24, 2010

Collaborative Engineering Approach Towards IP-Based SoC Design	Aug. 18, 2008

Straightforward IP Integration with IP-XACT RTL-TLM Switching	Jun. 26, 2008

Development and use of an Instruction Set Simulator of 68000-compatible processor core	Apr. 24, 2008

Transaction Level Model of the USB On-The-Go controller IP core	Jul. 23, 2007

Transaction Level Model of IEEE 1394 Serial Bus Link Layer Controller IP Core and its Use in the Software Driver Development	Apr. 03, 2006

Previous Headlines:

2024

Sep

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

2001

2000

1999

© 2024 Design And Reuse

All Rights Reserved.

No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse.

Partner with us

Partner with us

List your Products

Suppliers, list your IPs for free.

List your Products

Design-Reuse.com