Title Sign Up for SoC News Alert  |
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A Guide on Logical Equivalence Checking - Flow, Challenges, and Benefits |
Feb. 11, 2019 |
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Designing an Effective Traffic Management System Through Vehicle Classification and Counting Techniques |
Nov. 29, 2018 |
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System Verilog Assertions Simplified |
Oct. 22, 2018 |
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Implementing Parallel Processing and Fine Control in Design Verification |
Sep. 17, 2018 |
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Usage of Multibit Flip-Flop and its Challenges in ASIC Physical Design |
Jul. 23, 2018 |
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Aircraft Jet Engine Failure Analytics Using Google Cloud Platform Based Deep Learning |
Apr. 09, 2018 |
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SoC Functional verification flow |
Dec. 21, 2017 |
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Wind Turbine Fault Detection Using Machine Learning And Neural Networks |
Dec. 18, 2017 |
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Ins and Outs of Assertion in Mixed Signal Verification |
Nov. 06, 2017 |
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Platform Software Verification Framework Solution for Safety Critical Systems |
Oct. 23, 2017 |
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Smart Tracking of SoC Verification Progress Using Synopsys' Hierarchical Verification Plan (HVP) |
Oct. 09, 2017 |
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Processor-In-Loop Simulation: Embedded Software Verification & Validation In Model Based Development |
Aug. 28, 2017 |
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UVM Sequence Library - Usage, Advantages, and Limitations |
Aug. 14, 2017 |
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Power Optimization using Multi BIT flops and MIMCAPs in 16nm technology and below |
Jun. 26, 2017 |
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Correlation of Routability and Placement Density for better QoR in 16nm technology |
May. 15, 2017 |
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Verification Planner in QuestaSim |
Apr. 03, 2017 |
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Applying DevOps to IoT solution development |
Mar. 07, 2017 |
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Design Rule Checks (DRC) - A Practical View for 28nm Technology |
Feb. 27, 2017 |
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API-based verification: Effective reuse of verification environment components |
Feb. 24, 2017 |
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A Review Paper on CMOS, SOI and FinFET Technology |
Feb. 01, 2017 |
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Understanding the Technology behind Traffic Sign Recognition (TSR) Systems |
Jan. 03, 2017 |
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Power of UVM's Command Line Argument Usage in Verification Test benches |
Oct. 20, 2016 |
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Verification "escapes" leave bugs in silicon |
Sep. 13, 2016 |
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Resets in FPGA & ASIC control and data paths |
Sep. 05, 2016 |
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Advanced BLDC Motor Control using Freescale Ultra Reliable MPC5676R/MPC5674F MCU |
Aug. 15, 2016 |
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Platform Software Verification Approaches For Safety Critical Systems |
Jul. 04, 2016 |
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ATPG Challenges at Lower Technology Nodes |
May. 23, 2016 |
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High bandwidth memory (HBM) PHY IP verification |
Feb. 24, 2016 |
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DFT strategy for IPs |
Jan. 11, 2016 |
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Multiple clock domain SoCs: Verification techniques |
Oct. 27, 2014 |
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Boundary scan: Seven benefits |
Jun. 26, 2014 |
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The need for speed in low latency video system designs |
Jun. 17, 2014 |
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Leakage power optimization for 28nm and beyond |
Apr. 24, 2014 |
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Impact of wire resistance in advance technology |
Feb. 17, 2014 |
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Smart Transit Solution |
Dec. 02, 2013 |
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Digital Signal Processing (DSP) Verification |
Sep. 16, 2013 |
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Bridging the Gap: Pre to Post Silicon Functional Validation |
Sep. 09, 2013 |
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Extreme Programming |
Aug. 19, 2013 |
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Low Power Design for Testability |
Jun. 17, 2013 |
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Soft memories in PD flow : Myth and Reality |
May. 28, 2013 |
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Generic DDR Behavioural Model |
May. 20, 2013 |
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System Test using JTAG |
Apr. 15, 2013 |
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Analog Mixed Signal Verification Methodology (AMSVM) |
Jan. 30, 2012 |
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Hardware Co-Verification using VMM HAL-SCEMI On ChipIT Platform |
Mar. 07, 2011 |
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A monitor-based approach to verification |
Jun. 02, 2010 |
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Guidelines for complex SoC verification |
Feb. 16, 2010 |
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Using an FPGA to tame the power beast in consumer handheld MPUs |
Jan. 18, 2010 |
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HDL Design Methods for Low-Power Implementation |
May. 28, 2009 |
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Migrating from SPI 4.2 to SPI 5 IP Core - Architectural Changes and Re-usability |
Feb. 09, 2009 |
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System Packet Interface (SPI) 4.2 IP Core |
Apr. 28, 2008 |
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Complex SoC Verification using ARM Processor |
Mar. 01, 2007 |
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