IEEE 802.15.4- 2011 - MAC and PHY
TICO-XS (JPEG XS) 4K Encoder / Decoder IP-core
130nm FTP Non Volatile Memory for Standard CMOS Logic Process
Real-Time-Clock with calendar, timer and alarm functions.
Expedera Introduces Its Origin Neural Engine IP With Unrivaled Energy-Efficiency and Performance
PLDA Introduces a Complete Line of PCIe IP for USB4, Enabling PCIe Support in USB4 Hubs, Hosts and Devices
Logic Design Solutions Introduces the first NVMe HOST IP on POLARFIRE SoC FPGA
A short primer on instruction set architecture
Building security into an AI SoC using CPU features with extensions
Paving the way for the next generation audio codec for True Wireless Stereo (TWS) applications - Optimizing latency key factor
What is an ASIP?
Design IP Sales Grew 16.7% in 2020, Best Growth Rate Ever!
SiFive RISC-V Proven in 5nm Silicon
© 2021 Design And Reuse
All Rights Reserved.
No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse.
Suppliers, list your IPs for free.