Introduction
With an unprecedented need for ever-increasing performance, scalability, high-yield, and heterogeneous integration, HPC, AI/ML, and automotive chip designers are turning to multi-die design architectures to deliver their demanding requirements and QoR targets. Through the advent of chiplets, heterogeneous integration, dedicated IP subsystems, and 2.5D/3D advanced packaging technology, multi-die designs have become the go-to solution for creating advanced silicon chips.
Challenges
Developing a multi-die design introduces numerous additional steps and challenges from architectural specification through logical and physical design to verification and signoff. Designing in three dimensions adds complex die-to-die interconnects – logical and physical. Whether the architecture is 3D stacking, 2.5D interposers, or organic substrates, there can be millions of inter-die interconnects that must be created, assigned, debugged and validated. Ensuring that these interconnects are logically and physically correct and meet all complex inter-die design rules is very challenging.
As designs grow larger and become increasingly complex, chip designers need graphical visualizations of their designs in EDA tools. Today these include logic schematics and physical layout views. In a multi-die design, advanced visualizations are even more important as it becomes more difficult to visualize aspects of the design in three dimensions. Interconnect visualization is critical to efficiently track down, identify, and fix interconnect and cross-die related issues. Those issues can include:
- Contacting die bump or bonding pad alignment issues
- Missing/extra bumps
- Interconnect logical-physical consistency issues
- Incomplete path from backside bump to TSV to frontside bump
- Incomplete path through contacting dies