For more than five decades, the semiconductor industry advanced along a remarkably predictable path. Moore’s Law guided transistor scaling, while Dennard scaling ensured that reducing dimensions automatically delivered improvements in performance, power efficiency, and density. Each new technology node brought faster transistors, lower operating voltages, reduced interconnect delay, and higher integration density.
During this period, physical design and custom chip design flow benefited enormously from scaling. As transistors became smaller, interconnects naturally shortened. Timing improved almost automatically, power density remained manageable, and routing complexity was largely proportional to design size. The role of physical design focused on optimization rather than limitation.
In early CMOS generations, technology node names had direct physical meaning. A 180nm or 65nm process accurately reflected gate length or metal pitch. Shrinking geometry improved nearly every aspect of chip behaviour in unison.
This predictable relationship began to weaken as the industry approached the 28nm node. At around 28 nm, planar CMOS scaling encountered fundamental physical barriers. Short-channel effects intensified, leakage currents rose sharply, and process variability became increasingly difficult to control. Further reductions in channel length no longer produced proportional performance gains.
From this point forward, technology node names transitioned from physical measurements to generational labels. Although nodes such as 7nm, 5nm, 3nm and 2nm suggest aggressive shrinkage, the actual physical gate lengths changed only modestly. Gate lengths that were already close to 30 nm at 28 nm reduced to around 18 to 20nm at 7nm, and approximately 10 to 12 nm at 5 nm. Beyond this, scaling slowed dramatically.
Yet transistor density continued to increase. This was made possible by a fundamental shift from geometric scaling to architectural scaling.
Beyond Channel Length: How Transistors Continue to Improve
The industry moved away from planar MOSFETs and introduced three-dimensional transistor structures that enhance electrostatic control and current drive without aggressive channel length reduction. This shift fundamentally changed the meaning of scaling.
The first major architectural breakthrough was the FinFET. Instead of forming the transistor channel horizontally on the substrate, FinFETs introduced a vertical silicon fin around which the gate wrapped on three sides. This structure significantly improved electrostatic control over the channel.
FinFET technology enabled lower leakage, reduced short-channel effects, and better performance at reduced voltages. It successfully extended CMOS scaling from the 22nm node through the 7nm generation and became the industry standard for nearly a decade.
However, FinFET scaling eventually reached its own limits. As fins became narrower, carrier mobility degraded, and variability increased. Increasing fin height introduced mechanical and manufacturability challenges, while adding more fins resulted in quantized transistor sizing that limited optimization flexibility. As gate lengths continued to shrink, the electrostatic advantage of the fin structure also began to erode.
These limitations made it clear that simply refining FinFETs was no longer enough. Continued scaling demanded a stronger form of gate control, paving the way for GAAFET architectures as the next major transistor transition.