Analogix Semiconductor is a global provider of mixed-signal semiconductors, committed to advancing display quality on mobile devices while maximizing battery efficiency. Guided by their vision of “HD everywhere”, Analogix develops proprietary intellectual property using industry-standard interfaces to maintain circuit compatibility across targeted applications.
In September 2025, at the Solido Custom IC Forum in Beijing, Analogix demonstrated how they leveraged Solido SPICE to address challenges associated with phase-locked loop (PLL) design—a critical clocking component for high-performance display and connectivity solutions.
Challenges
PLL plays a key role in numerous systems, particularly in SerDes, where it supplies a stable clock for tasks like serialization, deserialization, jitter reduction, and frequency synthesis to accommodate various communication standards. As a result, having a high-quality PLL is essential for maintaining overall SerDes system stability. However, designing high-quality PLLs at Analogix faces three key challenges, primarily due to semiconductor advancements and strict noise performance requirements. Let’s discuss these challenges in detail:
Challenge 1: Device count
The required number of devices in a PLL rises swiftly as a result of fabrication limitations. These constraints drive the need to incorporate more devices into the design to achieve the desired performance and reliability levels. To ensure optimal matching and minimize noise, analog circuits must utilize complex compound devices. This complexity is essential for meeting the stringent requirements of advanced PLL designs, especially as noise performance becomes increasingly critical. Furthermore, device models are growing more intricate, often involving effects that extend beyond the capabilities of conventional Berkeley short-channel IGFET models (BSIM). As semiconductor technology progresses, capturing these advanced behaviors becomes necessary to accurately predict and optimize PLL performance.