2.5D advanced packaging is becoming increasingly critical as the demand for AI and high-performance computing (HPC) applications continues to rise and monolithic die size hits reticle limit. To sustain continuous growth in computing performance, advanced packaging technologies are constantly evolving. TSMC's System-on-Wafer (TSMC-SoW™) technology and its highly advanced design necessitate a reliable and efficient high-performance electromagnetic (EM) analysis tool.
Design Optimization for SerDes Beyond 200G Interconnects and PDNs with Clarity 3D Solver
CadenceLIVE 2026 included a presentation by Cadence customer Global Unichip Corp. (GUC) discussing how GUC uses Clarity 3D Solver and Sigrity X PowerSI analysis technologies to perform signal integrity/power integrity (SI/PI) simulations for high-speed key IP on SoW-X, including serializer/deserializer (SerDes) 212G, GUC's Universal Chiplet Interconnect Express (GUCIe) D2D 64G, and more. An example is provided showing how the Clarity solver is used to analyze the signal integrity of the SerDes 212G signals on SoW-X. Through the visualized EM field provided by the tool, the near-end crosstalk (NEXT) at the micro bump (μBump) and ball-grid array (BGA) interfaces is strengthened from approximately −46dB (failed spec. −65dB) to about −74dB (pass spec.), while the far-end crosstalk (FEXT) is improved from approximately −27dB (failed spec. −40dB) to about −60dB (pass spec.).